Pub Date : 2022-11-21DOI: 10.1109/SBESC56799.2022.9965177
Angelo Elias Dalzotto, Caroline da Silva Borges, Marcelo Ruaro, F. Moraes
Many-core Systems on Chip (MCSoCs) require resource management to achieve scalability at the computation and communication levels. The monitoring infrastructure feeds management tasks with raw data, enabling these tasks to detect behaviors corresponding to constraint violations or a trend that signalizes a future violation. Several works available in the literature use monitoring to apply their management techniques but do not specify how to implement the monitoring framework. We propose a monitoring framework for MCSoCs, with the following features: (i) generic: the infrastructure can carry data related to different monitored features; (ii) monitored data does not disturb NoC flows; and (iii) reduced overhead compared to other monitoring methods. The monitoring framework is loosely coupled to the MCSoC by using a dedicated NoC to carry monitoring and management messages, decoupling data traffic from management traffic. Results adopt the Observe-Decide-Act management method, comparing the proposed monitoring framework to a standard monitoring approach. Results show a reduction in the data NoC traffic (12%), faster management responsiveness to act on deadline violations (up to 77%), and reduced applications execution time (on average 8%).
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Pub Date : 2022-11-21DOI: 10.1109/SBESC56799.2022.9964880
Electronic memories are subject to failure due to magnetic fields and radiation, causing temporary faults that can be mitigated by error correction codes. Evaluating the efficacy of these mechanisms in hardware can make the design more expensive, take a long prototyping time, and even lose time to market. Hardware simulators or emulators are often generic, requiring specific and specialized development to evaluate memory controllers. This work proposes Absimth to assess the computational system behavior in the presence of memory errors. Absimth is a hardware simulator focusing on memory controller data flow, allowing the creation and configuration of custom modules. The simulator aims to optimize the design of next-generation memory controller architectures, meeting fault tolerance requirements with fast validation before the hardware implementation phases.
{"title":"Assessing Rules in Memory Controllers with Hardware Simulator Executing Real Programs","authors":"","doi":"10.1109/SBESC56799.2022.9964880","DOIUrl":"https://doi.org/10.1109/SBESC56799.2022.9964880","url":null,"abstract":"Electronic memories are subject to failure due to magnetic fields and radiation, causing temporary faults that can be mitigated by error correction codes. Evaluating the efficacy of these mechanisms in hardware can make the design more expensive, take a long prototyping time, and even lose time to market. Hardware simulators or emulators are often generic, requiring specific and specialized development to evaluate memory controllers. This work proposes Absimth to assess the computational system behavior in the presence of memory errors. Absimth is a hardware simulator focusing on memory controller data flow, allowing the creation and configuration of custom modules. The simulator aims to optimize the design of next-generation memory controller architectures, meeting fault tolerance requirements with fast validation before the hardware implementation phases.","PeriodicalId":130479,"journal":{"name":"2022 XII Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129175850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-17DOI: 10.1109/CLUSTER.2003.10006
M. d’Aquin, B. Ganter, D. Ignatov, S. Obiedkov
Steven Alter, University of San Francisco Joseph Barjis, Delft University of Technology Nivedita P Deshmukh, Infosys Ltd. Marlon Dumas, University of Tartu Schahram Dustdar, TU Wien Claude Godart, Loria Daniela Grigori, Laboratoire LAMSADE, University Paris-Dauphine Hunter Hastings, Hult Business School Junichi Iijima, Tokyo Institute of Technology Marta Indulska, The University of Queensland Agnes Koschmider, Karlsruher Institute of Technology Torsten Leiding, SAP Fabrizio Maggi, University of Tartu Prabir Nandi, IBM Research Daniel Oberle, SAP Manfred Reichert, University of Ulm Hajo A. Reijers, Eindhoven University of Technology Stefanie Rinderle-Ma, University of Vienna Stefan Sackmann, University of Halle-Wittenberg Jeff Saperstein, Hult Business School Venky Shankararaman, Singapore Management University Farouk Toumani, Limos, Blaise Pascal University, Clermont-Ferrand Guido Wirtz, University of Bamberg
{"title":"Program Committee","authors":"M. d’Aquin, B. Ganter, D. Ignatov, S. Obiedkov","doi":"10.1109/CLUSTER.2003.10006","DOIUrl":"https://doi.org/10.1109/CLUSTER.2003.10006","url":null,"abstract":" Steven Alter, University of San Francisco Joseph Barjis, Delft University of Technology Nivedita P Deshmukh, Infosys Ltd. Marlon Dumas, University of Tartu Schahram Dustdar, TU Wien Claude Godart, Loria Daniela Grigori, Laboratoire LAMSADE, University Paris-Dauphine Hunter Hastings, Hult Business School Junichi Iijima, Tokyo Institute of Technology Marta Indulska, The University of Queensland Agnes Koschmider, Karlsruher Institute of Technology Torsten Leiding, SAP Fabrizio Maggi, University of Tartu Prabir Nandi, IBM Research Daniel Oberle, SAP Manfred Reichert, University of Ulm Hajo A. Reijers, Eindhoven University of Technology Stefanie Rinderle-Ma, University of Vienna Stefan Sackmann, University of Halle-Wittenberg Jeff Saperstein, Hult Business School Venky Shankararaman, Singapore Management University Farouk Toumani, Limos, Blaise Pascal University, Clermont-Ferrand Guido Wirtz, University of Bamberg","PeriodicalId":130479,"journal":{"name":"2022 XII Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130528849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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