Pub Date : 2024-12-04DOI: 10.1109/jssc.2024.3506781
Guangshu Zhao, Chao Xie, Chenxi Wang, Milin Zhang, Man-Kay Law
{"title":"High-Efficiency Ultrasound Energy Harvesting Interface With Auto-Calibrated Timing Control From $-$25 $^{circ}$C to 85 $^{circ}$C","authors":"Guangshu Zhao, Chao Xie, Chenxi Wang, Milin Zhang, Man-Kay Law","doi":"10.1109/jssc.2024.3506781","DOIUrl":"https://doi.org/10.1109/jssc.2024.3506781","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"19 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142776420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/JSSC.2024.3504546
Yan He;Yumin Su;Kaiyuan Yang
Fault injection attacks (FIAs) induce hardware failures in circuits and exploit these faults to compromise the security of the system. It has been demonstrated that FIAs can bypass system security mechanisms, cause faulty outputs, and gain access to secret information. Certain types of FIAs can be mounted with little effort by tampering with clock signals and/or the chip’s operating conditions. To mitigate such low-cost, yet powerful attacks, we propose a fully synthesizable and distributable in situ fault injection monitor that employs a delay locked loop (DLL) to track the pulsewidth of the clock. We further develop a fully automated design framework to optimize and implement the FIA monitors at any process node. Our design is fabricated and verified in 65-nm CMOS technology with a small footprint of $1500~{mu }$ m2. It can lock to clock frequencies from 2 MHz to 1.26 GHz while detecting all 12 types of possible clock glitches, as well as timing FIA injections via the supply voltage, electromagnetic (EM) signals, and chip temperature.
{"title":"Design-Agnostic Distributed Timing Fault Injection Monitor With End-to-End Design Automation","authors":"Yan He;Yumin Su;Kaiyuan Yang","doi":"10.1109/JSSC.2024.3504546","DOIUrl":"10.1109/JSSC.2024.3504546","url":null,"abstract":"Fault injection attacks (FIAs) induce hardware failures in circuits and exploit these faults to compromise the security of the system. It has been demonstrated that FIAs can bypass system security mechanisms, cause faulty outputs, and gain access to secret information. Certain types of FIAs can be mounted with little effort by tampering with clock signals and/or the chip’s operating conditions. To mitigate such low-cost, yet powerful attacks, we propose a fully synthesizable and distributable in situ fault injection monitor that employs a delay locked loop (DLL) to track the pulsewidth of the clock. We further develop a fully automated design framework to optimize and implement the FIA monitors at any process node. Our design is fabricated and verified in 65-nm CMOS technology with a small footprint of <inline-formula> <tex-math>$1500~{mu }$ </tex-math></inline-formula>m2. It can lock to clock frequencies from 2 MHz to 1.26 GHz while detecting all 12 types of possible clock glitches, as well as timing FIA injections via the supply voltage, electromagnetic (EM) signals, and chip temperature.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":"146-157"},"PeriodicalIF":4.6,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142776374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/jssc.2024.3501196
Pietro Salvi, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino
{"title":"A Low-Noise Fractional-$N$ Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC","authors":"Pietro Salvi, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino","doi":"10.1109/jssc.2024.3501196","DOIUrl":"https://doi.org/10.1109/jssc.2024.3501196","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"78 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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