Pub Date : 2024-09-20DOI: 10.1109/jssc.2024.3456865
Seung-Beom Ku, Jinhyoung Kim, Kwonhong Lee, Han-Sol Lee, Kyeongho Eom, Minju Park, Cheolung Cha, Hyung-Min Lee
{"title":"An RF MEMS Sensor Driver/Readout SoC With Resonant Frequency Shift and Closed-Loop Envelope Regulation for Portable Microplastic Detection","authors":"Seung-Beom Ku, Jinhyoung Kim, Kwonhong Lee, Han-Sol Lee, Kyeongho Eom, Minju Park, Cheolung Cha, Hyung-Min Lee","doi":"10.1109/jssc.2024.3456865","DOIUrl":"https://doi.org/10.1109/jssc.2024.3456865","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"199 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142275476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-20DOI: 10.1109/JSSC.2024.3458463
Haoran Li;Tailong Xu;Xi Meng;Jun Yin;Rui P. Martins;Pui-In Mak
This article presents a type-II sub-sampling phase-locked loop (SSPLL) that achieves low jitter, low spur, and sub- $mu $ s locking time when synthesizing millimeter-wave (mm-wave) frequencies. The proposed function-reused (FR) voltage-controlled oscillator (VCO)-buffer eliminates the noise and capacitive loading from the transistors in the buffer, improving the jitter and reference (ref.) spur of the SSPLL simultaneously. It also eliminates the inductor typically employed in the high-frequency buffer, reducing the chip area. The proposed low-power fast frequency-locked loop (FLL) utilizes a phase aligner to decouple the dependency of the locking time on the initial phase error. The FLL also employs a coarse-fine-time-to-digital converter (TDC)-based type-I loop for promptly searching the control word of the switched capacitors (SCs). This article also details the analysis of the ref. spur and the phase noise (PN) performance using the FR VCO-buffer as well as the design considerations of the proposed FLL. Fabricated in 28-nm CMOS, the SSPLL occupies a compact area of 0.065 mm2 and achieves an rms jitter of 48.3 fs at 26 GHz while consuming 19.1 mW, corresponding to excellent FoMJ and FoMN of −253.5 and −277.6 dB, respectively. The measured ref. spur is −66 dBc, and the measured locking time at a frequency jump from 0.4 to 2.8 GHz is within 55 ref. cycles.
{"title":"A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment","authors":"Haoran Li;Tailong Xu;Xi Meng;Jun Yin;Rui P. Martins;Pui-In Mak","doi":"10.1109/JSSC.2024.3458463","DOIUrl":"10.1109/JSSC.2024.3458463","url":null,"abstract":"This article presents a type-II sub-sampling phase-locked loop (SSPLL) that achieves low jitter, low spur, and sub-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000s locking time when synthesizing millimeter-wave (mm-wave) frequencies. The proposed function-reused (FR) voltage-controlled oscillator (VCO)-buffer eliminates the noise and capacitive loading from the transistors in the buffer, improving the jitter and reference (ref.) spur of the SSPLL simultaneously. It also eliminates the inductor typically employed in the high-frequency buffer, reducing the chip area. The proposed low-power fast frequency-locked loop (FLL) utilizes a phase aligner to decouple the dependency of the locking time on the initial phase error. The FLL also employs a coarse-fine-time-to-digital converter (TDC)-based type-I loop for promptly searching the control word of the switched capacitors (SCs). This article also details the analysis of the ref. spur and the phase noise (PN) performance using the FR VCO-buffer as well as the design considerations of the proposed FLL. Fabricated in 28-nm CMOS, the SSPLL occupies a compact area of 0.065 mm2 and achieves an rms jitter of 48.3 fs at 26 GHz while consuming 19.1 mW, corresponding to excellent FoMJ and FoMN of −253.5 and −277.6 dB, respectively. The measured ref. spur is −66 dBc, and the measured locking time at a frequency jump from 0.4 to 2.8 GHz is within 55 ref. cycles.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"3952-3965"},"PeriodicalIF":4.6,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142275461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/JSSC.2024.3456190
Ji Jin;Weiwei Xu;Lin Cheng
This article presents a compact single-inductor bipolar-output (SIBO) converter for active-matrix organic light-emitting diode (AMOLED) displays. Addressing the demand for a large load capacity within a limited form factor, we propose a hybrid SIBO converter featuring two flying capacitors ( $C_{mathrm {F}}$ s) which are introduced to further reduce the inductor current ( ${I} _{mathrm {L}}$ ) and voltage stress of power switches. The proposed converter mainly consists of two operation states that determine the energy charging and distribution, respectively, when the two outputs have the same load currents. To address potential loading imbalance, two auxiliary phases are incorporated into the main operation states. A concise PWM control strategy, consisting of a common-mode (CM) loop and differential-mode (DM) loop, is also proposed for bipolar output regulation with fast transient responses. The converter is fabricated in a 0.18- $mu $ m BCD process and the measured peak efficiency reaches 94.5% using a $2.5times 2.0times 1.2$ mm3 inductor. Furthermore, the converter achieves 3.99 W/mm2 on-die power density with the total off-chip components occupying 15.32-mm3 volume, demonstrating that this design provides a compact solution for AMOLED displays.
{"title":"A Hybrid Single-Inductor Bipolar-Output Converter With a Concise PWM Control for AMOLED Displays","authors":"Ji Jin;Weiwei Xu;Lin Cheng","doi":"10.1109/JSSC.2024.3456190","DOIUrl":"10.1109/JSSC.2024.3456190","url":null,"abstract":"This article presents a compact single-inductor bipolar-output (SIBO) converter for active-matrix organic light-emitting diode (AMOLED) displays. Addressing the demand for a large load capacity within a limited form factor, we propose a hybrid SIBO converter featuring two flying capacitors (\u0000<inline-formula> <tex-math>$C_{mathrm {F}}$ </tex-math></inline-formula>\u0000s) which are introduced to further reduce the inductor current (\u0000<inline-formula> <tex-math>${I} _{mathrm {L}}$ </tex-math></inline-formula>\u0000) and voltage stress of power switches. The proposed converter mainly consists of two operation states that determine the energy charging and distribution, respectively, when the two outputs have the same load currents. To address potential loading imbalance, two auxiliary phases are incorporated into the main operation states. A concise PWM control strategy, consisting of a common-mode (CM) loop and differential-mode (DM) loop, is also proposed for bipolar output regulation with fast transient responses. The converter is fabricated in a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m BCD process and the measured peak efficiency reaches 94.5% using a \u0000<inline-formula> <tex-math>$2.5times 2.0times 1.2$ </tex-math></inline-formula>\u0000 mm3 inductor. Furthermore, the converter achieves 3.99 W/mm2 on-die power density with the total off-chip components occupying 15.32-mm3 volume, demonstrating that this design provides a compact solution for AMOLED displays.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"4150-4161"},"PeriodicalIF":4.6,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142245699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a fractional-N digital phase-locked loop (DPLL) characterized by low jitter and small area, featuring fast multi-variable calibration. To minimize the use of silicon area, the LC voltage-controlled oscillator (VCO) incorporated a compact three-turn inductor. Then, to still achieve low jitter, the bandwidth of the PLL was designed to be wide to suppress the poor phase noise of this VCO. To mitigate in-band noise, a digital-to-time converter (DTC) was employed to cancel the quantization noise (Q-noise) from the $Delta Sigma $ M, and a phase selector (PSEL) was used to reduce the thermal noise of the DTC. The effectiveness of these jitter-reduction techniques relies on digital background calibration. However, conventional multi-variable calibrators (MVCs), which utilize the least-mean-squares (LMS) algorithm, suffer from a prolonged convergence time. To overcome this limitation, this work introduced a recursive least-squares (RLS)-based MVC using a dichotomous coordinate descent (DCD) algorithm that can facilitate rapid calibration at a moderate implementation cost. The proposed DCD-RLS MVC achieved a calibration time of less than $7.2~{mu }$ s, which was 40 times faster than the LMS MVC. The DPLL of this work achieved 88 fsrms jitter at a near-integer-N channel with 68-dBc fractional spurs. Fabricated using a 40-nm CMOS process, it occupied only a 0.12-mm2 active area and consumed 15.7 mW of power.
{"title":"A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm","authors":"Seheon Jang;Munjae Chae;Hangi Park;Chanwoong Hwang;Jaehyouk Choi","doi":"10.1109/JSSC.2024.3456105","DOIUrl":"10.1109/JSSC.2024.3456105","url":null,"abstract":"This work presents a fractional-N digital phase-locked loop (DPLL) characterized by low jitter and small area, featuring fast multi-variable calibration. To minimize the use of silicon area, the LC voltage-controlled oscillator (VCO) incorporated a compact three-turn inductor. Then, to still achieve low jitter, the bandwidth of the PLL was designed to be wide to suppress the poor phase noise of this VCO. To mitigate in-band noise, a digital-to-time converter (DTC) was employed to cancel the quantization noise (Q-noise) from the \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000M, and a phase selector (PSEL) was used to reduce the thermal noise of the DTC. The effectiveness of these jitter-reduction techniques relies on digital background calibration. However, conventional multi-variable calibrators (MVCs), which utilize the least-mean-squares (LMS) algorithm, suffer from a prolonged convergence time. To overcome this limitation, this work introduced a recursive least-squares (RLS)-based MVC using a dichotomous coordinate descent (DCD) algorithm that can facilitate rapid calibration at a moderate implementation cost. The proposed DCD-RLS MVC achieved a calibration time of less than \u0000<inline-formula> <tex-math>$7.2~{mu }$ </tex-math></inline-formula>\u0000s, which was 40 times faster than the LMS MVC. The DPLL of this work achieved 88 fsrms jitter at a near-integer-N channel with 68-dBc fractional spurs. Fabricated using a 40-nm CMOS process, it occupied only a 0.12-mm2 active area and consumed 15.7 mW of power.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"3884-3897"},"PeriodicalIF":4.6,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142245934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/JSSC.2024.3414159
Xiaodong Meng;Xing Li;Chi-Ying Tsui;Wing-Hung Ki;Weiqiang Liu
A primary driver with a fractional capacitance (FC) auto-tuning loop (ATL) for wireless-powered biomedical devices is presented. The proposed ATL maintains the resonance of the primary LC tank against varying inductance over a wide range in real time. The analog ATL has a wide loop bandwidth and achieves phase locking within six cycles. The fractional capacitor is realized with a switch-controlled capacitor. By varying the turn-on time of the switch, the effective capacitance is changed, which tunes the resonant frequency of the primary LC tank. The primary driver is a full-bridge Class-D power amplifier (PA). High-side NMOS power switches are driven by bootstrap circuits. An adaptive offset controller is proposed to compensate for the delays of comparators to enhance tuning accuracy. The chip is fabricated using a 0.18- $mu $ m bipolar-CMOS-DMOS (BCD) process, and the active area is 0.66 mm2. The system operates at 13.56 MHz and maintains both zero-voltage switching (ZVS) and zero-current switching (ZCS) in a steady state. The maximum PA output power is 200 mW, the measured tuning range is 31.5%, and the tuning error is 1.89 ns.
{"title":"A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices","authors":"Xiaodong Meng;Xing Li;Chi-Ying Tsui;Wing-Hung Ki;Weiqiang Liu","doi":"10.1109/JSSC.2024.3414159","DOIUrl":"10.1109/JSSC.2024.3414159","url":null,"abstract":"A primary driver with a fractional capacitance (FC) auto-tuning loop (ATL) for wireless-powered biomedical devices is presented. The proposed ATL maintains the resonance of the primary LC tank against varying inductance over a wide range in real time. The analog ATL has a wide loop bandwidth and achieves phase locking within six cycles. The fractional capacitor is realized with a switch-controlled capacitor. By varying the turn-on time of the switch, the effective capacitance is changed, which tunes the resonant frequency of the primary LC tank. The primary driver is a full-bridge Class-D power amplifier (PA). High-side NMOS power switches are driven by bootstrap circuits. An adaptive offset controller is proposed to compensate for the delays of comparators to enhance tuning accuracy. The chip is fabricated using a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m bipolar-CMOS-DMOS (BCD) process, and the active area is 0.66 mm2. The system operates at 13.56 MHz and maintains both zero-voltage switching (ZVS) and zero-current switching (ZCS) in a steady state. The maximum PA output power is 200 mW, the measured tuning range is 31.5%, and the tuning error is 1.89 ns.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 10","pages":"3218-3231"},"PeriodicalIF":4.6,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142236581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/JSSC.2024.3439865
Haidam Choi;Song-I Cheon;Gichan Yun;Sein Oh;Ji-Hoon Suh;Sohmyung Ha;Minkyu Je
This article presents a bio-impedance (bioZ) readout IC featuring a complex-domain noise-correlated baseline cancellation to overcome the limitation of the conventional baseline cancellation with the real-domain noise correlation. The proposed technique is especially beneficial in cases with significant phase shifts between the excitation current from the current generator (CG) and the input voltage signal produced across the bioZ, through which the CG current flows. This technique employs a tunable reference impedance (TRI) and adaptively adjusts it to match the bioZ in both magnitude and phase, thereby achieving a complex-domain correlation of CG noise. By flowing an identical CG current through both the TRI and bioZ, the noise voltages across the TRI and bioZ caused by the CG current become closely correlated with each other, even in the presence of substantial phase shifts, enabling effective CG noise removal after baseline subtraction. Furthermore, this work proposes a differential-difference current-balancing instrumentation amplifier (DD-CBIA) with quiet chopping for baseline subtraction, offering low power consumption, wide input range, and low input-dependent noise. Measurement results demonstrate significant enhancements in noise performance by a factor of 2.47 and 4.88 for the bioZs with phases of 30° and 60°, respectively, achieving a signal-to-noise ratio (SNR) of 101.5 dB and a figure of merit (FoM) of 150.0 dB. Validation through human-subject experiments using two-electrode configurations on the chest and wrist further supports the effectiveness of the proposed bioZ readout IC.
本文介绍了一种生物阻抗（bioZ）读出集成电路，它具有复域噪声相关基线消除功能，克服了传统的实域噪声相关基线消除功能的局限性。在电流发生器（CG）产生的激励电流与生物振荡器上产生的输入电压信号（CG 电流流经生物振荡器）之间存在明显相位偏移的情况下，所提出的技术尤为有利。该技术采用了可调参考阻抗 (TRI)，并对其进行自适应调整，使其在幅度和相位上与生物区相匹配，从而实现了 CG 噪声的复域相关性。通过在 TRI 和生物 Z 之间流过相同的 CG 电流，CG 电流在 TRI 和生物 Z 上引起的噪声电压变得彼此密切相关，即使存在较大的相位偏移，也能在基线减除后有效去除 CG 噪声。此外，这项研究还提出了一种差分电流平衡仪表放大器（DD-CBIA），具有用于基线减法的静音斩波功能，功耗低、输入范围宽、输入相关噪声低。测量结果表明，相位分别为 30° 和 60° 的生物 Z 的噪声性能显著提高了 2.47 倍和 4.88 倍，信噪比 (SNR) 达到 101.5 dB，优越性 (FoM) 达到 150.0 dB。通过使用胸部和手腕上的双电极配置进行人体实验验证，进一步证明了拟议生物区读出集成电路的有效性。
{"title":"A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation","authors":"Haidam Choi;Song-I Cheon;Gichan Yun;Sein Oh;Ji-Hoon Suh;Sohmyung Ha;Minkyu Je","doi":"10.1109/JSSC.2024.3439865","DOIUrl":"10.1109/JSSC.2024.3439865","url":null,"abstract":"This article presents a bio-impedance (bioZ) readout IC featuring a complex-domain noise-correlated baseline cancellation to overcome the limitation of the conventional baseline cancellation with the real-domain noise correlation. The proposed technique is especially beneficial in cases with significant phase shifts between the excitation current from the current generator (CG) and the input voltage signal produced across the bioZ, through which the CG current flows. This technique employs a tunable reference impedance (TRI) and adaptively adjusts it to match the bioZ in both magnitude and phase, thereby achieving a complex-domain correlation of CG noise. By flowing an identical CG current through both the TRI and bioZ, the noise voltages across the TRI and bioZ caused by the CG current become closely correlated with each other, even in the presence of substantial phase shifts, enabling effective CG noise removal after baseline subtraction. Furthermore, this work proposes a differential-difference current-balancing instrumentation amplifier (DD-CBIA) with quiet chopping for baseline subtraction, offering low power consumption, wide input range, and low input-dependent noise. Measurement results demonstrate significant enhancements in noise performance by a factor of 2.47 and 4.88 for the bioZs with phases of 30° and 60°, respectively, achieving a signal-to-noise ratio (SNR) of 101.5 dB and a figure of merit (FoM) of 150.0 dB. Validation through human-subject experiments using two-electrode configurations on the chest and wrist further supports the effectiveness of the proposed bioZ readout IC.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 11","pages":"3538-3548"},"PeriodicalIF":4.6,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142236580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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