Pub Date : 2024-10-01DOI: 10.1109/JSSC.2024.3462296
Soroush Araei;Negar Reiskarimian
This article covers a synthesizing methodology for addressing harmonic rejection (HR) in hard-switching passive mixers. The integration of bottom and top plate mixing provides HR at both the antenna node and the output of the mixer in a passive and low-loss manner. A prototype mixer-first receiver (RX) in 45-nm partially depleted silicon-on-insulator (PD-SOI) is implemented, consuming 34.8–64.5 mW for clock frequencies ( $f_{text {LO}}$ ) of 0.25–4 GHz and occupying an active area of 0.68 mm2. Due to the passive and early HR, it achieves an exceptional in-band (IB) harmonic blocker 1-dB compression point (B1 dB) of +14/+16.5 dBm at the third/fifth harmonics at a clock frequency of 1 GHz. Notably, with blocker powers up to 5 and 6.5 dBm at $3f_{text {LO}}$ and $5f_{text {LO}}$ , respectively, the harmonic blocker noise figure (BNF) only deteriorates by 3 dB at a clock frequency of 1 GHz. The minimal overhead of components facilitates the seamless incorporation of HR in widely tunable RXs and benefits from scaling.
{"title":"Implementation and Application of Harmonic Reset Switching in Passive Mixers","authors":"Soroush Araei;Negar Reiskarimian","doi":"10.1109/JSSC.2024.3462296","DOIUrl":"10.1109/JSSC.2024.3462296","url":null,"abstract":"This article covers a synthesizing methodology for addressing harmonic rejection (HR) in hard-switching passive mixers. The integration of bottom and top plate mixing provides HR at both the antenna node and the output of the mixer in a passive and low-loss manner. A prototype mixer-first receiver (RX) in 45-nm partially depleted silicon-on-insulator (PD-SOI) is implemented, consuming 34.8–64.5 mW for clock frequencies (\u0000<inline-formula> <tex-math>$f_{text {LO}}$ </tex-math></inline-formula>\u0000) of 0.25–4 GHz and occupying an active area of 0.68 mm2. Due to the passive and early HR, it achieves an exceptional in-band (IB) harmonic blocker 1-dB compression point (B1 dB) of +14/+16.5 dBm at the third/fifth harmonics at a clock frequency of 1 GHz. Notably, with blocker powers up to 5 and 6.5 dBm at \u0000<inline-formula> <tex-math>$3f_{text {LO}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$5f_{text {LO}}$ </tex-math></inline-formula>\u0000, respectively, the harmonic blocker noise figure (BNF) only deteriorates by 3 dB at a clock frequency of 1 GHz. The minimal overhead of components facilitates the seamless incorporation of HR in widely tunable RXs and benefits from scaling.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"4009-4021"},"PeriodicalIF":4.6,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142362841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/JSSC.2024.3462093
Haijun Shao;Rui P. Martins;Pui-In Mak
This article reports a 2.4-GHz Bluetooth low-energy (BLE) receiver with a number of passive-intensive RF functions to improve power efficiency and blocker resilience. It features a passive quadrature front end (QFE) built with a hybrid coupler plus two step-up transformers. They passively provide input-impedance matching, voltage gain, and single-ended-to-differential-I/Q RF generation. The four-phase RF outputs simplify the LO generator into a 2.4-GHz class-D voltage-controlled oscillator (VCO) that has an intrinsically boosted output swing, averting the power-hungry divider-by-2 and LO buffers. The frequency down-conversion based on a double-sided double-balanced (DSDB) cascaded mixer offers a high passive gain to reduce the noise and power consumption of the baseband (BB) circuitry while securing a high spurious-free dynamic range (SFDR) to tolerate the out-of-band (OOB) blockers. The BB circuitry is a power-efficient hybrid low-IF filter that employs a 2nd-order active-feedback notching to enhance the 1st-adjacent channel rejection. Fabricated in 28-nm CMOS, the BLE receiver exhibits a maximum RF-to-IF gain of 71 dB. The noise figure (NF) is 8.5 dB and the OOB-IIP3 is 20.1 dBm; they correspond to a 71.7-dB SFDR for a 2-MHz BLE channel and a 10-dB minimum signal-to-noise ratio (SNR $_{min }$ ). The VCO exhibits a phase noise (PN) of −110/−119.1/−131 dBc/Hz at 1-/2.5-/10-MHz offset, corresponding to a figure of merit (FOM) of 188/189/189.1 dBc/Hz, respectively. The total power consumption of the receiver, including the VCO, is $167~{mu }$ W.
本文介绍了一种 2.4 GHz 低功耗蓝牙 (BLE) 接收器，它具有许多无源密集型射频功能，可提高能效和抗阻塞性。它采用无源正交前端 (QFE)，内置一个混合耦合器和两个升压变压器。它们无源提供输入阻抗匹配、电压增益和单端到差分 I/Q 射频生成。四相射频输出将 LO 发生器简化为 2.4 GHz 的 D 类压控振荡器 (VCO)，该振荡器具有固有的升压输出摆幅，避免了耗电的 2 分频器和 LO 缓冲器。基于双面双平衡（DSDB）级联混频器的频率下变频具有较高的无源增益，可降低基带（BB）电路的噪声和功耗，同时确保较高的无杂散动态范围（SFDR），以承受带外（OOB）阻塞。基带电路是一种高能效混合低中频滤波器，采用二阶有源反馈陷波来增强一相邻信道抑制能力。BLE 接收器采用 28 纳米 CMOS 制造，最大射频到中频增益为 71 dB。噪声系数（NF）为 8.5 dB，OOB-IIP3 为 20.1 dBm；对应于 2 MHz BLE 信道的 71.7 dB SFDR 和 10 dB 最小信噪比（SNR $_{min }$ ）。在 1-/2.5-/10-MHz 偏移时，VCO 的相位噪声 (PN) 为-110/-119.1/-131 dBc/Hz，分别相当于 188/189/189.1 dBc/Hz。接收器（包括 VCO）的总功耗为 167~{mu }$ W。
{"title":"A 167- μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double- Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO","authors":"Haijun Shao;Rui P. Martins;Pui-In Mak","doi":"10.1109/JSSC.2024.3462093","DOIUrl":"10.1109/JSSC.2024.3462093","url":null,"abstract":"This article reports a 2.4-GHz Bluetooth low-energy (BLE) receiver with a number of passive-intensive RF functions to improve power efficiency and blocker resilience. It features a passive quadrature front end (QFE) built with a hybrid coupler plus two step-up transformers. They passively provide input-impedance matching, voltage gain, and single-ended-to-differential-I/Q RF generation. The four-phase RF outputs simplify the LO generator into a 2.4-GHz class-D voltage-controlled oscillator (VCO) that has an intrinsically boosted output swing, averting the power-hungry divider-by-2 and LO buffers. The frequency down-conversion based on a double-sided double-balanced (DSDB) cascaded mixer offers a high passive gain to reduce the noise and power consumption of the baseband (BB) circuitry while securing a high spurious-free dynamic range (SFDR) to tolerate the out-of-band (OOB) blockers. The BB circuitry is a power-efficient hybrid low-IF filter that employs a 2nd-order active-feedback notching to enhance the 1st-adjacent channel rejection. Fabricated in 28-nm CMOS, the BLE receiver exhibits a maximum RF-to-IF gain of 71 dB. The noise figure (NF) is 8.5 dB and the OOB-IIP3 is 20.1 dBm; they correspond to a 71.7-dB SFDR for a 2-MHz BLE channel and a 10-dB minimum signal-to-noise ratio (SNR\u0000<inline-formula> <tex-math>$_{min }$ </tex-math></inline-formula>\u0000). The VCO exhibits a phase noise (PN) of −110/−119.1/−131 dBc/Hz at 1-/2.5-/10-MHz offset, corresponding to a figure of merit (FOM) of 188/189/189.1 dBc/Hz, respectively. The total power consumption of the receiver, including the VCO, is \u0000<inline-formula> <tex-math>$167~{mu }$ </tex-math></inline-formula>\u0000W.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"3980-3992"},"PeriodicalIF":4.6,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142362838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/jssc.2024.3460426
Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Kyogu Lee, Dongsuk Jeon
{"title":"A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS","authors":"Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Kyogu Lee, Dongsuk Jeon","doi":"10.1109/jssc.2024.3460426","DOIUrl":"https://doi.org/10.1109/jssc.2024.3460426","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"41 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142325245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/JSSC.2024.3459392
Niels Fakkel;Luc Enthoven;Jiwon Yun;Margriet van Riggelen;Hendrik Benjamin van Ommen;Kai-Niklas Schymik;Hans P. Bartling;Eftychia Tsapanou Katranara;René Vollmer;Tim H. Taminiau;Masoud Babaie;Fabio Sebastiano
Striving toward a scalable quantum processor, this article presents the first cryo-CMOS quantum bit (qubit) controller targeting color centers in diamond. Color-center qubits enable a modular architecture that allows for the 3-D integration of photonics, cryo-CMOS control electronics, and qubits in the same package. However, performing quantum operations in a scalable manner requires large currents in the driving coils due to low coil-to-qubit coupling. Moreover, active calibration of the qubit Larmor frequency is required to compensate inhomogeneities of the bias magnetic field. To overcome these challenges, this work proposes both a cryo-CMOS alternating current (AC) controller consisting of a class-DE series-resonant driver and a DC current regulator (DC CR) that uses a triode-biased H-bridge for scalable low-power qubit operations. By experimentally validating the cryo-CMOS performance with a nitrogen-vacancy (NV) color-center qubit, the AC controller can drive a Rabi oscillation up to 2.5 MHz with a supply draw of 6.5 mA, and the DC CR can tune the Larmor frequency by ±9 MHz while driving up to ±20 mA in the bias coil. $T_{2}^{*}$ coherence times up to $5.3~mu $ s and single-qubit gate fidelities above 98% are demonstrated with the cryo-CMOS control using Ramsey experiments and gate set tomography (GST), respectively. The results demonstrate the efficacy of the proposed cryo-CMOS chips and enable the development of a modular quantum processor based on color centers.
为了实现可扩展的量子处理器，本文介绍了首个针对金刚石色彩中心的低温-CMOS 量子位（量子位）控制器。色彩中心量子比特采用模块化架构，可将光子学、低温-CMOS 控制电子器件和量子比特三维集成在同一封装中。然而，由于线圈与量子比特之间的耦合度较低，以可扩展的方式执行量子操作需要在驱动线圈中注入大电流。此外，还需要主动校准量子比特的拉莫尔频率，以补偿偏置磁场的不均匀性。为了克服这些挑战，这项研究提出了一种低温-CMOS 交流电（AC）控制器，该控制器由一个 DE 类串联谐振驱动器和一个直流电流调节器（DC CR）组成，后者使用一个三极管偏置 H 桥，用于可扩展的低功耗量子比特操作。通过使用氮空位（NV）色心量子比特对低温-CMOS 性能进行实验验证，交流控制器可以驱动高达 2.5 MHz 的拉比振荡，耗电仅为 6.5 mA，而直流电流调节器可以将拉莫尔频率调整为 ±9 MHz，同时在偏置线圈中驱动高达 ±20 mA 的电流。 利用拉姆齐实验和栅极层析成像（GST），低温-CMOS 控制的 $T_{2}^{*}$ 相干时间可达 5.3~mu $ s，单量子比特栅极保真度超过 98%。这些结果证明了所提出的低温-CMOS 芯片的功效，并使基于色彩中心的模块化量子处理器的开发成为可能。
{"title":"A Cryo-CMOS Controller With Class-DE Driver and DC Magnetic-Field Tuning for Quantum Computers Based on Color Centers in Diamond","authors":"Niels Fakkel;Luc Enthoven;Jiwon Yun;Margriet van Riggelen;Hendrik Benjamin van Ommen;Kai-Niklas Schymik;Hans P. Bartling;Eftychia Tsapanou Katranara;René Vollmer;Tim H. Taminiau;Masoud Babaie;Fabio Sebastiano","doi":"10.1109/JSSC.2024.3459392","DOIUrl":"10.1109/JSSC.2024.3459392","url":null,"abstract":"Striving toward a scalable quantum processor, this article presents the first cryo-CMOS quantum bit (qubit) controller targeting color centers in diamond. Color-center qubits enable a modular architecture that allows for the 3-D integration of photonics, cryo-CMOS control electronics, and qubits in the same package. However, performing quantum operations in a scalable manner requires large currents in the driving coils due to low coil-to-qubit coupling. Moreover, active calibration of the qubit Larmor frequency is required to compensate inhomogeneities of the bias magnetic field. To overcome these challenges, this work proposes both a cryo-CMOS alternating current (AC) controller consisting of a class-DE series-resonant driver and a DC current regulator (DC CR) that uses a triode-biased H-bridge for scalable low-power qubit operations. By experimentally validating the cryo-CMOS performance with a nitrogen-vacancy (NV) color-center qubit, the AC controller can drive a Rabi oscillation up to 2.5 MHz with a supply draw of 6.5 mA, and the DC CR can tune the Larmor frequency by ±9 MHz while driving up to ±20 mA in the bias coil. \u0000<inline-formula> <tex-math>$T_{2}^{*}$ </tex-math></inline-formula>\u0000 coherence times up to \u0000<inline-formula> <tex-math>$5.3~mu $ </tex-math></inline-formula>\u0000s and single-qubit gate fidelities above 98% are demonstrated with the cryo-CMOS control using Ramsey experiments and gate set tomography (GST), respectively. The results demonstrate the efficacy of the proposed cryo-CMOS chips and enable the development of a modular quantum processor based on color centers.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 11","pages":"3627-3643"},"PeriodicalIF":4.6,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695764","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142325247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-25DOI: 10.1109/JSSC.2024.3460178
Francesco Tesolin;Simone M. Dartizio;Giacomo Castoro;Francesco Buccoleri;Michele Rossoni;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino
This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave (FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the modulation signal. A new digital predistortion (DPD) algorithm is introduced that is specifically tailored to mitigate the impact of the nonlinear non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for a low phase noise. The algorithm estimates in the background a non-uniform piecewise parabolic (PWP) interpolation of the digital inverse of the DCO tuning curve, using an adaptive set of non-uniformly distributed breakpoints. The breakpoints are automatically placed at the corner points of the tuning characteristic. The chirp generator, implemented in a 28-nm CMOS process, dissipates 21 mW and generates sawtooth and triangular chirp frequency modulations with slope up to 680 MHz/ $mu $ s and bandwidth up to 680 MHz, while keeping the rms frequency error below 150 kHz and the phase noise at 1-MHz offset at −116.5 dBc/Hz.
{"title":"A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars","authors":"Francesco Tesolin;Simone M. Dartizio;Giacomo Castoro;Francesco Buccoleri;Michele Rossoni;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino","doi":"10.1109/JSSC.2024.3460178","DOIUrl":"10.1109/JSSC.2024.3460178","url":null,"abstract":"This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave (FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the modulation signal. A new digital predistortion (DPD) algorithm is introduced that is specifically tailored to mitigate the impact of the nonlinear non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for a low phase noise. The algorithm estimates in the background a non-uniform piecewise parabolic (PWP) interpolation of the digital inverse of the DCO tuning curve, using an adaptive set of non-uniformly distributed breakpoints. The breakpoints are automatically placed at the corner points of the tuning characteristic. The chirp generator, implemented in a 28-nm CMOS process, dissipates 21 mW and generates sawtooth and triangular chirp frequency modulations with slope up to 680 MHz/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 s and bandwidth up to 680 MHz, while keeping the rms frequency error below 150 kHz and the phase noise at 1-MHz offset at −116.5 dBc/Hz.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"3915-3927"},"PeriodicalIF":4.6,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142321708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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