Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605403
Intent-based networking (IBN) captures and translates business intent into network policies that can be automated and applied consistently across the network. The end goal is for the network to continuously monitor and adjust its performance to assure the desired business outcome. For network operators (NetOps), IBN simplifies management, improves security, and provides data and telemetry for assurance and diagnostics.
{"title":"Machine Reasoning — Improving AIOps for Intent Based Networks","authors":"","doi":"10.1109/nas51552.2021.9605403","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605403","url":null,"abstract":"Intent-based networking (IBN) captures and translates business intent into network policies that can be automated and applied consistently across the network. The end goal is for the network to continuously monitor and adjust its performance to assure the desired business outcome. For network operators (NetOps), IBN simplifies management, improves security, and provides data and telemetry for assurance and diagnostics.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123906387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper studies utilizing the growing family of solid-state drives (SSDs) with built-in transparent compression to simplify the data structure of cache design. Such storage hardware allows the user applications to intentionally under-utilize logical storage space (i.e., sparse LBA utilization, and sparse storage block content) without sacrificing the physical storage space. Accordingly, this work proposed an index-less cache management approach to largely simplify the flash-based cache management by leveraging SSDs with built-in transparent compression. We carried out various experiments to evaluate the write amplification and read performance of the proposed cache management, and the results show that our proposed indexless cache management can achieve comparable or much better performance than the conventional policies while consuming much less host computing and memory resources.
{"title":"Implementing Flash-Cached Storage Systems Using Computational Storage Drive with Built-in Transparent Compression","authors":"Jingpeng Hao, Xubin Chen, Yifan Qiao, Yuyang Zhang, Tong Zhang","doi":"10.1109/nas51552.2021.9605383","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605383","url":null,"abstract":"This paper studies utilizing the growing family of solid-state drives (SSDs) with built-in transparent compression to simplify the data structure of cache design. Such storage hardware allows the user applications to intentionally under-utilize logical storage space (i.e., sparse LBA utilization, and sparse storage block content) without sacrificing the physical storage space. Accordingly, this work proposed an index-less cache management approach to largely simplify the flash-based cache management by leveraging SSDs with built-in transparent compression. We carried out various experiments to evaluate the write amplification and read performance of the proposed cache management, and the results show that our proposed indexless cache management can achieve comparable or much better performance than the conventional policies while consuming much less host computing and memory resources.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122082785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605365
Rajorshi Biswas, Jie Wu
Link congestion due to regular traffic and link flooding attacks (LFA) are two major problems in datacenters. Recent usage growth of software defined networking (SDN) in datacenters enables dynamic and convenient configuration management that makes it easy to reconfigure the network to mitigate the LFA. The reconfiguration that redirects some of the traffic can be done in two ways: the shortest alternative path and the minimum changes in rule path. The SDN switches have a limited capacity for the rules and the performance dramatically drops when the number of stored rules is higher. Besides, it takes some time to adopt the changes by the SDN switches which causes interruption in flow. In this paper, we aim at minimizing the number of rule changes while redirecting some of the traffic from the congested link. We formulate two problems to minimize the number of rule changes to redirect traffic. The first problem is the basic and it considers a congested link and a flow to direct. We provide a Dijkstra-based and a rule merging based solution to the problems. The second problem considers multiple flows and we propose flow grouping and rule merging based solutions. We conduct extensive simulations and experiments in our datacenter to support our model.
{"title":"Minimizing the Number of Rules to Mitigate Link Congestion in SDN-based Datacenters","authors":"Rajorshi Biswas, Jie Wu","doi":"10.1109/nas51552.2021.9605365","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605365","url":null,"abstract":"Link congestion due to regular traffic and link flooding attacks (LFA) are two major problems in datacenters. Recent usage growth of software defined networking (SDN) in datacenters enables dynamic and convenient configuration management that makes it easy to reconfigure the network to mitigate the LFA. The reconfiguration that redirects some of the traffic can be done in two ways: the shortest alternative path and the minimum changes in rule path. The SDN switches have a limited capacity for the rules and the performance dramatically drops when the number of stored rules is higher. Besides, it takes some time to adopt the changes by the SDN switches which causes interruption in flow. In this paper, we aim at minimizing the number of rule changes while redirecting some of the traffic from the congested link. We formulate two problems to minimize the number of rule changes to redirect traffic. The first problem is the basic and it considers a congested link and a flow to direct. We provide a Dijkstra-based and a rule merging based solution to the problems. The second problem considers multiple flows and we propose flow grouping and rule merging based solutions. We conduct extensive simulations and experiments in our datacenter to support our model.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130298640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605434
Hadi Zamani, Devashree Tripathy, A. Jahanshahi, Daniel Wong
The leakage energy of GPGPU can be reduced by power gating the idle logic or undervolting the storage structures; however, the performance and reliability of the system degrades due to large wake up time and inrush current at time of activation. In this paper, we thoroughly analyze the realistic Break-Even Time (BET) and inrush current for various components in GPGPU architecture considering the recent design of multi-modal Power Gating Switch (PGS). Then, we introduce a new PGS which covers the current PGS drawbacks. Our redesigned PGS is carefully tailored to minimize the inrush current and BET. GPGPU-Sim simulation results for various applications, show that, with incorporating the proposed PGS into GPGPU-Sim, we can save leakage energy up to 82%, 38%, and 60% for register files, integer units, and floating units respectively.
{"title":"ICAP: Designing Inrush Current Aware Power Gating Switch for GPGPU","authors":"Hadi Zamani, Devashree Tripathy, A. Jahanshahi, Daniel Wong","doi":"10.1109/nas51552.2021.9605434","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605434","url":null,"abstract":"The leakage energy of GPGPU can be reduced by power gating the idle logic or undervolting the storage structures; however, the performance and reliability of the system degrades due to large wake up time and inrush current at time of activation. In this paper, we thoroughly analyze the realistic Break-Even Time (BET) and inrush current for various components in GPGPU architecture considering the recent design of multi-modal Power Gating Switch (PGS). Then, we introduce a new PGS which covers the current PGS drawbacks. Our redesigned PGS is carefully tailored to minimize the inrush current and BET. GPGPU-Sim simulation results for various applications, show that, with incorporating the proposed PGS into GPGPU-Sim, we can save leakage energy up to 82%, 38%, and 60% for register files, integer units, and floating units respectively.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122424022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605411
Devashree Tripathy, AmirAli Abdolrashidi, Quan Fan, Daniel Wong, M. Satpathy
Exploiting data locality in GPGPUs is critical for efficiently using the smaller data caches and handling the memory bottleneck problem. This paper proposes a thread block-centric locality analysis, which identifies the locality among the thread blocks (TBs) in terms of a number of common data references. In LocalityGuru, we seek to employ a detailed just-in-time (JIT) compilation analysis of the static memory accesses in the source code and derive the mapping between the threads and data indices at kernel-launch-time. Our locality analysis technique can be employed at multiple granularities such as threads, warps, and thread blocks in a GPU Kernel. This information can be leveraged to help make smarter decisions for locality-aware data-partition, memory page data placement, cache management, and scheduling in single-GPU and multi-GPU systems.The results of the LocalityGuru PTX analyzer are then validated by comparing with the Locality graph obtained through profiling. Since the entire analysis is carried out by the compiler before the kernel launch time, it does not introduce any timing overhead to the kernel execution time.
{"title":"LocalityGuru: A PTX Analyzer for Extracting Thread Block-level Locality in GPGPUs","authors":"Devashree Tripathy, AmirAli Abdolrashidi, Quan Fan, Daniel Wong, M. Satpathy","doi":"10.1109/nas51552.2021.9605411","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605411","url":null,"abstract":"Exploiting data locality in GPGPUs is critical for efficiently using the smaller data caches and handling the memory bottleneck problem. This paper proposes a thread block-centric locality analysis, which identifies the locality among the thread blocks (TBs) in terms of a number of common data references. In LocalityGuru, we seek to employ a detailed just-in-time (JIT) compilation analysis of the static memory accesses in the source code and derive the mapping between the threads and data indices at kernel-launch-time. Our locality analysis technique can be employed at multiple granularities such as threads, warps, and thread blocks in a GPU Kernel. This information can be leveraged to help make smarter decisions for locality-aware data-partition, memory page data placement, cache management, and scheduling in single-GPU and multi-GPU systems.The results of the LocalityGuru PTX analyzer are then validated by comparing with the Locality graph obtained through profiling. Since the entire analysis is carried out by the compiler before the kernel launch time, it does not introduce any timing overhead to the kernel execution time.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116749802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605470
Tanay Roy, Jit Gupta, K. Kant, Amitangshu Pal, D. Minturn, Arash Tavakkol
Solid-State Drives (SSDs) involve a complex set of management activities in the background, resulting in unpredictable delays and occasional extended access latencies. However, there is an increasing demand for "deterministic" access latency in a growing number of scenarios. This demand has prompted a new feature in the NVMe storage access protocol called Predictable Latency Mode (PLM), which provides a way to tighten tail latency in SSDs. This paper presents the first study of the PLM feature in a single-host environment and its extension to multi-host settings. We propose a PLM Coordinator (PLMC) that regulates access to the PLM of a shared SSD device based on the hosts’ traffic characteristics. Our simulation experiments show that the proposed PLMC can achieve 82% improvement in 99.99% tail latency compared to a bare SSD without PLM feature. Moreover, the proposed coordinator with simple traffic prediction can perform 93.2% better than without coordinator on the 99%-tail latency values.
{"title":"PLMC: A Predictable Tail Latency Mode Coordinator for Shared NVMe SSD with Multiple Hosts","authors":"Tanay Roy, Jit Gupta, K. Kant, Amitangshu Pal, D. Minturn, Arash Tavakkol","doi":"10.1109/nas51552.2021.9605470","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605470","url":null,"abstract":"Solid-State Drives (SSDs) involve a complex set of management activities in the background, resulting in unpredictable delays and occasional extended access latencies. However, there is an increasing demand for \"deterministic\" access latency in a growing number of scenarios. This demand has prompted a new feature in the NVMe storage access protocol called Predictable Latency Mode (PLM), which provides a way to tighten tail latency in SSDs. This paper presents the first study of the PLM feature in a single-host environment and its extension to multi-host settings. We propose a PLM Coordinator (PLMC) that regulates access to the PLM of a shared SSD device based on the hosts’ traffic characteristics. Our simulation experiments show that the proposed PLMC can achieve 82% improvement in 99.99% tail latency compared to a bare SSD without PLM feature. Moreover, the proposed coordinator with simple traffic prediction can perform 93.2% better than without coordinator on the 99%-tail latency values.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114837888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605422
Yeim-Kuan Chang, Hung-Yen Wang, Yu-Hsiang Lin
The equal-cost multi-path routing (ECMP) [4] achieves load balance in data centers network. Without network’s congestion status, ECMP may cause significant imbalance between paths. In this paper, we propose a better congestion aware routing protocol for Software Defined Network (SDN) to provide a better average link utilization. We follow the idea of In-band Network Telemetry (INT) to collect link congestion status in data center networks. Edge switches are responsible for detecting elephant flows by running a heavy hitter detection algorithm. When an elephant flow is reported to the controller by an edge switch, controller will use the collected congestion status to find the least congested path. In order to make the switches forward packets more efficiently and reduce the number of rules in switches’ forwarding table, we adopt label switching. We develop a Programming Protocol-independent Packet Processors (P4) program to design our novel routing scheme, which contains a heavy hitter detection algorithm. We further validate that our heavy hitter detection algorithm can run on Banzai machine. We also write a Python controller to communicate with P4 switches through P4 Runtime protocol. Our experimental results shows that the probing process in CAMP minimizes the bandwidth overhead in data centers. We use Mininet to construct fat-tree topologies and the emulated software P4switches run BMv2. The data mining workload is used to generate the traffic in our experiment. CAMP achieves better FCT compared to ECMP and HULA [6]. Also, the number of routing rules in CAMP maintains the smallest when network grows.
{"title":"A Congestion Aware Multi-Path Label Switching in Data Centers Using Programmable Switches","authors":"Yeim-Kuan Chang, Hung-Yen Wang, Yu-Hsiang Lin","doi":"10.1109/nas51552.2021.9605422","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605422","url":null,"abstract":"The equal-cost multi-path routing (ECMP) [4] achieves load balance in data centers network. Without network’s congestion status, ECMP may cause significant imbalance between paths. In this paper, we propose a better congestion aware routing protocol for Software Defined Network (SDN) to provide a better average link utilization. We follow the idea of In-band Network Telemetry (INT) to collect link congestion status in data center networks. Edge switches are responsible for detecting elephant flows by running a heavy hitter detection algorithm. When an elephant flow is reported to the controller by an edge switch, controller will use the collected congestion status to find the least congested path. In order to make the switches forward packets more efficiently and reduce the number of rules in switches’ forwarding table, we adopt label switching. We develop a Programming Protocol-independent Packet Processors (P4) program to design our novel routing scheme, which contains a heavy hitter detection algorithm. We further validate that our heavy hitter detection algorithm can run on Banzai machine. We also write a Python controller to communicate with P4 switches through P4 Runtime protocol. Our experimental results shows that the probing process in CAMP minimizes the bandwidth overhead in data centers. We use Mininet to construct fat-tree topologies and the emulated software P4switches run BMv2. The data mining workload is used to generate the traffic in our experiment. CAMP achieves better FCT compared to ECMP and HULA [6]. Also, the number of routing rules in CAMP maintains the smallest when network grows.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122963711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605407
Tong Liu, Shakeel Alibhai, Jinzhen Wang, Qing Liu, Xubin He
As the storage overhead of high-performance computing (HPC) data reaches into the petabyte or even exabyte scale, it could be useful to find new methods of compressing such data. The compression autoencoder (CAE) has recently been proposed to compress HPC data with a very high compression ratio. However, this machine learning-based method suffers from the major drawback of lengthy training time. In this paper, we attempt to mitigate this problem by proposing a proportioning scheme to reduce the amount of data that is used for training relative to the amount of data to be compressed. We show that this method drastically reduces the training time without, in most cases, significantly increasing the error. We further explain how this scheme can even improve the accuracy of the CAE on certain datasets. Finally, we provide some guidance on how to determine a suitable proportion of the training dataset to use in order to train the CAE for a given dataset.
{"title":"Reducing the Training Overhead of the HPC Compression Autoencoder via Dataset Proportioning","authors":"Tong Liu, Shakeel Alibhai, Jinzhen Wang, Qing Liu, Xubin He","doi":"10.1109/nas51552.2021.9605407","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605407","url":null,"abstract":"As the storage overhead of high-performance computing (HPC) data reaches into the petabyte or even exabyte scale, it could be useful to find new methods of compressing such data. The compression autoencoder (CAE) has recently been proposed to compress HPC data with a very high compression ratio. However, this machine learning-based method suffers from the major drawback of lengthy training time. In this paper, we attempt to mitigate this problem by proposing a proportioning scheme to reduce the amount of data that is used for training relative to the amount of data to be compressed. We show that this method drastically reduces the training time without, in most cases, significantly increasing the error. We further explain how this scheme can even improve the accuracy of the CAE on certain datasets. Finally, we provide some guidance on how to determine a suitable proportion of the training dataset to use in order to train the CAE for a given dataset.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123007187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605388
As digitalization continues and sensors proliferate across every part of our world, the amount of data grows exponentially and demands for 3V (Volume, Velocity, Variety) storage systems accelerate. Cloud computing and big data applications have created a huge storage market that grows faster than ever before. The emerging of 5G cellular networks will make data growth even much faster. Besides the exponential growth of data volumes, big data applications require high performance, high reliability, security, high availability, and recoverability.
{"title":"Making Storage and SSD Smarter and Faster","authors":"","doi":"10.1109/nas51552.2021.9605388","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605388","url":null,"abstract":"As digitalization continues and sensors proliferate across every part of our world, the amount of data grows exponentially and demands for 3V (Volume, Velocity, Variety) storage systems accelerate. Cloud computing and big data applications have created a huge storage market that grows faster than ever before. The emerging of 5G cellular networks will make data growth even much faster. Besides the exponential growth of data volumes, big data applications require high performance, high reliability, security, high availability, and recoverability.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124444072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/nas51552.2021.9605428
Lei Sun, Q. Cao, Shucheng Wang, Changsheng Xie
Large-scale cloud storage systems use the logging mechanism to sequentially write data in an append-only manner. The write stream needs to be first appended and persisted into logging files, and then encoded with erasure coding (EC) in underlying storage. This introduces significant overhead to small write operations. To solve this problem, we propose EFLOG, a full-streaming storage framework that combines Logging and inter-log EC mechanisms. EFLOG evenly schedules front-end write streams across log files in each disk with append-only manner. In background, EFLOG determines unprotected logged data and seals them into ECblocks. Afterwards, EFLOG concurrently encodes data with multi-threads and stores parity data into parity disks. Results of our trace-driven evaluation show that, EFLOG can achieve up to 1.01GB/s write throughput with RS(4, 2) codes built upon 6 SSD disks.
{"title":"EFLOG: A Full Stream-Logging Scheme with Erasure Coding in Cloud Storage Systems","authors":"Lei Sun, Q. Cao, Shucheng Wang, Changsheng Xie","doi":"10.1109/nas51552.2021.9605428","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605428","url":null,"abstract":"Large-scale cloud storage systems use the logging mechanism to sequentially write data in an append-only manner. The write stream needs to be first appended and persisted into logging files, and then encoded with erasure coding (EC) in underlying storage. This introduces significant overhead to small write operations. To solve this problem, we propose EFLOG, a full-streaming storage framework that combines Logging and inter-log EC mechanisms. EFLOG evenly schedules front-end write streams across log files in each disk with append-only manner. In background, EFLOG determines unprotected logged data and seals them into ECblocks. Afterwards, EFLOG concurrently encodes data with multi-threads and stores parity data into parity disks. Results of our trace-driven evaluation show that, EFLOG can achieve up to 1.01GB/s write throughput with RS(4, 2) codes built upon 6 SSD disks.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132101241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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