This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limited-bandwidth communication link in the presence of data corrupting noise. Specifically we designed an asynchronous high-speed turbo decoder that can be potentially used for new wireless communications protocols with close to OC-12 throughputs. The design has been implemented using a new static single-track-full-buffer (SSTFB) standard cell library in IBM 0.18 mum technology that provides low latency, fast cycle-time, and more robustness to noise than previously studied single-track full-buffer technology (STFB). A high-speed synchronous counterpart using the same high-speed architecture is designed in the same technology for comparison. The results demonstrate that for a variety of network constraints, the asynchronous design provides advantages in throughput per area. Moreover, the asynchronous design can support very low-latency network constraints not achievable with the synchronous alternative.
{"title":"Design of a High-Speed Asynchronous Turbo Decoder","authors":"P. Golani, G. Dimou, M. Prakash, P. Beerel","doi":"10.1109/ASYNC.2007.16","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.16","url":null,"abstract":"This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limited-bandwidth communication link in the presence of data corrupting noise. Specifically we designed an asynchronous high-speed turbo decoder that can be potentially used for new wireless communications protocols with close to OC-12 throughputs. The design has been implemented using a new static single-track-full-buffer (SSTFB) standard cell library in IBM 0.18 mum technology that provides low latency, fast cycle-time, and more robustness to noise than previously studied single-track full-buffer technology (STFB). A high-speed synchronous counterpart using the same high-speed architecture is designed in the same technology for comparison. The results demonstrate that for a variety of network constraints, the asynchronous design provides advantages in throughput per area. Moreover, the asynchronous design can support very low-latency network constraints not achievable with the synchronous alternative.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121436183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VLSI systems are often constructed from a multitude of independently clocked synchronous IP blocks. Unfortunately, while a synchronous design style may produce efficient block level implementations it does little to support their composition. The addition of asynchronous interfaces to each synchronous block is one way to simplify and strengthen their integration. Asynchronous interfaces allow blocks to be composed without the need to consider synchronisation failure rates, permit data-driven operation and provide greater freedom when designing on-chip buses and networks. This paper surveys the significant body of published work in this area. We highlight similarities between schemes that are often concealed by differences in specification or circuit style. We also present new local clock implementations and provide solutions to mitigate the effect of clock-tree insertion delays. The ultimate goal of this work is to permit multi-clock synchronous systems to be composed simply, robustly and efficiently.
{"title":"Demystifying Data-Driven and Pausible Clocking Schemes","authors":"R. Mullins, S. Moore","doi":"10.1109/ASYNC.2007.15","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.15","url":null,"abstract":"VLSI systems are often constructed from a multitude of independently clocked synchronous IP blocks. Unfortunately, while a synchronous design style may produce efficient block level implementations it does little to support their composition. The addition of asynchronous interfaces to each synchronous block is one way to simplify and strengthen their integration. Asynchronous interfaces allow blocks to be composed without the need to consider synchronisation failure rates, permit data-driven operation and provide greater freedom when designing on-chip buses and networks. This paper surveys the significant body of published work in this area. We highlight similarities between schemes that are often concealed by differences in specification or circuit style. We also present new local clock implementations and provide solutions to mitigate the effect of clock-tree insertion delays. The ultimate goal of this work is to permit multi-clock synchronous systems to be composed simply, robustly and efficiently.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123128744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A long chain of inverters and wire segments will amplify clock jitter and drop timing pulses due to intersymbol interference. We present a jitter attenuating buffer based on surfing techniques. Our buffer circuit consists of a few inverters with variable output strength that implement a simple, low-gain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous interfaces. Furthermore, our chains can be used to reliably transmit handshaking signals and support sliding-window protocols to improve the throughput of asynchronous communication.
{"title":"A Jitter Attenuating Timing Chain","authors":"Suwen Yang, M. Greenstreet, Jihong Ren","doi":"10.1109/ASYNC.2007.8","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.8","url":null,"abstract":"A long chain of inverters and wire segments will amplify clock jitter and drop timing pulses due to intersymbol interference. We present a jitter attenuating buffer based on surfing techniques. Our buffer circuit consists of a few inverters with variable output strength that implement a simple, low-gain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous interfaces. Furthermore, our chains can be used to reliably transmit handshaking signals and support sliding-window protocols to improve the throughput of asynchronous communication.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129426072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, A. Kolodny
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.
{"title":"High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link","authors":"R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, A. Kolodny","doi":"10.1109/ASYNC.2007.20","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.20","url":null,"abstract":"A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114681524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Frankie Y. Liu, R. Ho, R. Drost, Scott M. Fairbanks
On-chip high-bandwidth sampling circuits supplement traditional test and debug techniques by non-invasively probing analog voltages for off-chip measurement. Existing circuits rely on sub-sampling techniques and thus require a synchronous clock. We extend these ideas to asynchronous circuits by combining an analog sampling head with a variable delay element and activating this circuit with an asynchronously triggered event. Repeated triggering events with different delays emulate sub-sampling. Simulations in a 180 nm technology of SRAM timing margins and GasP control failure modes show this technique can probe asynchronous signals with high fidelity.
{"title":"On-chip samplers for test and debug of asynchronous circuits","authors":"Frankie Y. Liu, R. Ho, R. Drost, Scott M. Fairbanks","doi":"10.1109/ASYNC.2007.24","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.24","url":null,"abstract":"On-chip high-bandwidth sampling circuits supplement traditional test and debug techniques by non-invasively probing analog voltages for off-chip measurement. Existing circuits rely on sub-sampling techniques and thus require a synchronous clock. We extend these ideas to asynchronous circuits by combining an analog sampling head with a variable delay element and activating this circuit with an asynchronously triggered event. Repeated triggering events with different delays emulate sub-sampling. Simulations in a 180 nm technology of SRAM timing margins and GasP control failure modes show this technique can probe asynchronous signals with high fidelity.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114591733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gwen Salaün, Wendelin Serwe, Y. Thonnart, P. Vivet
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architectures described in the high-level language CHP, by using model checking techniques provided by the CADP toolbox. Our proposal is based on an automatic translation from CHP into LOTOS, the process algebra used in CADP. A translator has been implemented, which handles full CHP including the specific probe operator. The CADP toolbox capabilities allow the designer to verify properties such as deadlock-freedom or protocol correctness on substantial systems. Our approach has been successfully applied to formally verify two complex designs. In this paper, we illustrate our technique on an asynchronous network-on-chip architecture. Its formal verification highlights the need to carefully design systems exhibiting non-deterministic behavior.
{"title":"Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip","authors":"Gwen Salaün, Wendelin Serwe, Y. Thonnart, P. Vivet","doi":"10.1109/ASYNC.2007.18","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.18","url":null,"abstract":"Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architectures described in the high-level language CHP, by using model checking techniques provided by the CADP toolbox. Our proposal is based on an automatic translation from CHP into LOTOS, the process algebra used in CADP. A translator has been implemented, which handles full CHP including the specific probe operator. The CADP toolbox capabilities allow the designer to verify properties such as deadlock-freedom or protocol correctness on substantial systems. Our approach has been successfully applied to formally verify two complex designs. In this paper, we illustrate our technique on an asynchronous network-on-chip architecture. Its formal verification highlights the need to carefully design systems exhibiting non-deterministic behavior.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125230582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, C. Myers, J. Keener
Synthetic biology uses engineering principles to design circuits out of genetic materials that are inserted into bacteria to perform various tasks. While synthetic combinational Boolean logic gates have been constructed, there are many open issues in the design of sequential logic gates. One such gate common in most asynchronous circuits is the Muller C-element, which is used to synchronize multiple independent processes. This paper proposes a novel design for a genetic Muller C-element using transcriptional regulatory elements. The design of a genetic Muller C-element enables the construction of virtually any asynchronous circuit from genetic material. There are, however, many issues that complicate designs with genetic materials. These complications result in modifications being required to the normal digital design procedure. This paper presents two designs that are logically equivalent to a Muller C-element. Mathematical analysis and stochastic simulation, however, show that only one functions reliably.
{"title":"The Design of a Genetic Muller C-Element","authors":"Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, C. Myers, J. Keener","doi":"10.1109/ASYNC.2007.27","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.27","url":null,"abstract":"Synthetic biology uses engineering principles to design circuits out of genetic materials that are inserted into bacteria to perform various tasks. While synthetic combinational Boolean logic gates have been constructed, there are many open issues in the design of sequential logic gates. One such gate common in most asynchronous circuits is the Muller C-element, which is used to synchronize multiple independent processes. This paper proposes a novel design for a genetic Muller C-element using transcriptional regulatory elements. The design of a genetic Muller C-element enables the construction of virtually any asynchronous circuit from genetic material. There are, however, many issues that complicate designs with genetic materials. These complications result in modifications being required to the normal digital design procedure. This paper presents two designs that are logically equivalent to a Muller C-element. Mathematical analysis and stochastic simulation, however, show that only one functions reliably.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134270310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Timing issues are a major concern in the design of high performance synchronous, asynchronous circuits and GALS. Investigations into the causes of many timing problems cannot be satisfactorily undertaken using external equipment due to its remoteness from the source of the potential problem; this necessitates the development of on-chip time measurement circuitry. Current techniques have the capability of resolving timing differences down to 5ps [1], however further improvement is impeded by process variations. This paper describes a flash Time to Digital Converter (TDC) suitable for on-chip implementation. The theory to overcome the effects of process variations, potentially permitting the time resolution down to one picosecond is described. Proof of concept is demonstrated by implementing the techniques in an FPGA, improving on the current resolution of FPGA implementation of a TDC.
{"title":"A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability","authors":"N. Minas, D. Kinniment, K. Heron, G. Russell","doi":"10.1109/ASYNC.2007.7","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.7","url":null,"abstract":"Timing issues are a major concern in the design of high performance synchronous, asynchronous circuits and GALS. Investigations into the causes of many timing problems cannot be satisfactorily undertaken using external equipment due to its remoteness from the source of the potential problem; this necessitates the development of on-chip time measurement circuitry. Current techniques have the capability of resolving timing differences down to 5ps [1], however further improvement is impeded by process variations. This paper describes a flash Time to Digital Converter (TDC) suitable for on-chip implementation. The theory to overcome the effects of process variations, potentially permitting the time resolution down to one picosecond is described. Proof of concept is demonstrated by implementing the techniques in an FPGA, improving on the current resolution of FPGA implementation of a TDC.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123301891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive protocols for global system-level communication. However, in practice, when designing asynchronous systems, it is extremely inefficient to build local computation nodes with two-phase logic, hence four-phase computation blocks are typically used. This paper proposes a new architecture, and circuit-level implementations, for a family of asynchronous protocol converters, which efficiently convert between two- and four-phase protocols, thus facilitating system design with robust global two-phase protocols and local four-phase protocols. The main focus is on a level-encoded dual-rail (LEDR) two-phase protocol for global communication, and a four-phase return-to-zero (RZ) protocol for asynchronous computation blocks. However, with small modifications, the converters are extended to handle other common four-phase protocols, such as 1- of-4 and single-rail bundled data. The converters are highly robust, with almost entirely quasi delay- insensitive implementations, yet exhibit high performance and modest area overhead. Initial post-layout simulations in a 0.18 micron TSMC process are provided, both assuming a small computation block (8times8 combinational multiplier) as well as an empty computation block (FIFO stage).
{"title":"Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication","authors":"Amit Mitra, William F. McLaughlin, S. Nowick","doi":"10.1109/ASYNC.2007.17","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.17","url":null,"abstract":"As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive protocols for global system-level communication. However, in practice, when designing asynchronous systems, it is extremely inefficient to build local computation nodes with two-phase logic, hence four-phase computation blocks are typically used. This paper proposes a new architecture, and circuit-level implementations, for a family of asynchronous protocol converters, which efficiently convert between two- and four-phase protocols, thus facilitating system design with robust global two-phase protocols and local four-phase protocols. The main focus is on a level-encoded dual-rail (LEDR) two-phase protocol for global communication, and a four-phase return-to-zero (RZ) protocol for asynchronous computation blocks. However, with small modifications, the converters are extended to handle other common four-phase protocols, such as 1- of-4 and single-rail bundled data. The converters are highly robust, with almost entirely quasi delay- insensitive implementations, yet exhibit high performance and modest area overhead. Initial post-layout simulations in a 0.18 micron TSMC process are provided, both assuming a small computation block (8times8 combinational multiplier) as well as an empty computation block (FIFO stage).","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124912471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a systematic and automated methodology is proposed for decomposing an asynchronous burst-mode (BM) controller into smaller sub-controllers, where each resulting sub-controller is activated on a communication channel. The proposed approach consists of a new decomposition algorithm, control micro-architecture and inter-controller communication protocol. This method has also been broadened to handle extended burst- mode (XBM) controllers. For both controller types, only a moderate amount of auxiliary hardware is required, and optimizations are proposed to eliminate or simplify this hardware. Initial runtime results for both burst-mode and extended burst- mode controllers are promising. Two of the largest BM benchmarks (dean-cache, scsi) were run using the Minimalist CAD tool and an optimized script. While the original controllers each timed out after 10 hours, the decomposition runs each completed in under 84 seconds. Further attempts to synthesize the original controllers using a suboptimal script succeeded, but with 16-200x greater runtime. Several XBM benchmarks were synthesized using the 3D CAD tool; one large complex controller (cdp-pl) was unable to complete while the decomposed run succeeded in under 197 seconds.
{"title":"A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers","authors":"Melinda Y. Agyekum, S. Nowick","doi":"10.1109/ASYNC.2007.6","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.6","url":null,"abstract":"In this paper, a systematic and automated methodology is proposed for decomposing an asynchronous burst-mode (BM) controller into smaller sub-controllers, where each resulting sub-controller is activated on a communication channel. The proposed approach consists of a new decomposition algorithm, control micro-architecture and inter-controller communication protocol. This method has also been broadened to handle extended burst- mode (XBM) controllers. For both controller types, only a moderate amount of auxiliary hardware is required, and optimizations are proposed to eliminate or simplify this hardware. Initial runtime results for both burst-mode and extended burst- mode controllers are promising. Two of the largest BM benchmarks (dean-cache, scsi) were run using the Minimalist CAD tool and an optimized script. While the original controllers each timed out after 10 hours, the decomposition runs each completed in under 84 seconds. Further attempts to synthesize the original controllers using a suboptimal script succeeded, but with 16-200x greater runtime. Several XBM benchmarks were synthesized using the 3D CAD tool; one large complex controller (cdp-pl) was unable to complete while the decomposed run succeeded in under 197 seconds.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127262125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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