The "Vortex" processor is a general purpose CPU with a novel architecture and instruction set. The primary feature of the Vortex architecture is many parallel function units which communicate through a central crossbar, instead of a traditional register file. Instructions are fetched in parallel by cache lines, as in a VLIW processor, but any data or structural dependencies are resolved deterministically by the hardware, as in a superscalar processor. The prototype Vortex CPU supports a 32-bit integer datapath and executes up to 9 instructions per cycle. It uses the "integrated pipelining" asynchronous design style, was fabricated in 2001 in TSMC's 0.15 mum G process, and runs at a typical frequency of 475MHz. Although the Vortex CPU itself has not been commercialized, many of its component circuits have been used in the products of Fulcrum Microsystems.
{"title":"The Vortex: A Superscalar Asynchronous Processor","authors":"Andrew Lines","doi":"10.1109/ASYNC.2007.28","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.28","url":null,"abstract":"The \"Vortex\" processor is a general purpose CPU with a novel architecture and instruction set. The primary feature of the Vortex architecture is many parallel function units which communicate through a central crossbar, instead of a traditional register file. Instructions are fetched in parallel by cache lines, as in a VLIW processor, but any data or structural dependencies are resolved deterministically by the hardware, as in a superscalar processor. The prototype Vortex CPU supports a 32-bit integer datapath and executes up to 9 instructions per cycle. It uses the \"integrated pipelining\" asynchronous design style, was fabricated in 2001 in TSMC's 0.15 mum G process, and runs at a typical frequency of 475MHz. Although the Vortex CPU itself has not been commercialized, many of its component circuits have been used in the products of Fulcrum Microsystems.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115320239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reports results of a study on pulse signaling. In pulse signaling, components communicate by means of pulses instead of voltage transitions. The functionality of the components is very similar to the functionality of components used in so-called asynchronous transition signalling. In asynchronous transition signalling, communication events are represented by voltage transitions, whereas in pulse signaling communication events are represented by pulses. We describe various implementations of pulse-signaling components, report on the energy efficiencies of our implementations, and look at some robustness aspects.
{"title":"Notes On Pulse Signaling","authors":"J. Ebergen, S. Furber, Arash Saifhashemi","doi":"10.1109/ASYNC.2007.23","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.23","url":null,"abstract":"This paper reports results of a study on pulse signaling. In pulse signaling, components communicate by means of pulses instead of voltage transitions. The functionality of the components is very similar to the functionality of components used in so-called asynchronous transition signalling. In asynchronous transition signalling, communication events are represented by voltage transitions, whereas in pulse signaling communication events are represented by pulses. We describe various implementations of pulse-signaling components, report on the energy efficiencies of our implementations, and look at some robustness aspects.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116128495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Microprocessors are employing higher levels of system integration for both higher performance and lower system cost. In doing so, problems that used to be apparent inter-device are now found intra- processor. The integration of the processor core with other units such as the north bridge often increase the number of clock domains within the device. In addition, the frequency of the external interfaces has increased at a much higher rate than the processor frequency. This trend will continue with the advent of multi-core processors which have increasing bandwidth demands. However, as the characteristics of the clock domains become more complex, the problem compounds the burden on the clock domain transfer mechanism to achieve low latency. Presented here is an easily implementable, low latency solution for clock domain transfer in the presence of high frequency mesochronous, plesiochronous, and heterochronous clock signaling.
{"title":"Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces","authors":"W. Williams, P. E. Madrid, Scott C. Johnson","doi":"10.1109/ASYNC.2007.21","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.21","url":null,"abstract":"Microprocessors are employing higher levels of system integration for both higher performance and lower system cost. In doing so, problems that used to be apparent inter-device are now found intra- processor. The integration of the processor core with other units such as the north bridge often increase the number of clock domains within the device. In addition, the frequency of the external interfaces has increased at a much higher rate than the processor frequency. This trend will continue with the advent of multi-core processors which have increasing bandwidth demands. However, as the characteristics of the clock domains become more complex, the problem compounds the burden on the clock domain transfer mechanism to achieve low latency. Presented here is an easily implementable, low latency solution for clock domain transfer in the presence of high frequency mesochronous, plesiochronous, and heterochronous clock signaling.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134058505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
FDR (failures-divergences refinement) is a tool for verifying properties of processes expressed in a machine-readable dialect of CSP (CSPM). This paper shows how to model asynchronous logic blocks as processes in CSPM and how to verify them using FDR: processes abstract away from the speed of the blocks; multi-way synchronization facilitates the modelling of isochronic forks; receptiveness is formalised as an assertion for FDR to check; process trans formations allow one to model transmission lines and handshaking ports. A process parameterised by a Boolean function suffices to model any complex gate; another such process models N-way mutual exclusion. The approach is illustrated on a variety of asynchronous circuits drawn from the literature.
{"title":"Gate-level modelling and verification of asynchronous circuits using CSPM and FDR","authors":"M. B. Josephs","doi":"10.1109/ASYNC.2007.19","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.19","url":null,"abstract":"FDR (failures-divergences refinement) is a tool for verifying properties of processes expressed in a machine-readable dialect of CSP (CSPM). This paper shows how to model asynchronous logic blocks as processes in CSPM and how to verify them using FDR: processes abstract away from the speed of the blocks; multi-way synchronization facilitates the modelling of isochronic forks; receptiveness is formalised as an assertion for FDR to check; process trans formations allow one to model transmission lines and handshaking ports. A process parameterised by a Boolean function suffices to model any complex gate; another such process models N-way mutual exclusion. The approach is illustrated on a variety of asynchronous circuits drawn from the literature.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132237938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Andrew M. Scott, M. Schuelein, M. Roncken, Jin-Jer Hwan, J. Bainbridge, John Mawer, D. L. Jackson, A. Bardsley
For today's SoC designer, on-die variation, clock distribution, timing closure, and power concerns confront the desire to get products to market quicker. Each new process generation makes the challenge greater as process skews, complexity, and frequency become more onerous. This is particularly true for signals that have to travel across larger portions of a chip such as clocks and buses. In this paper, we examine the use of GALS (Globally Asynchronous, Locally Synchronous) [Chapiro, 1985] techniques to address on-chip communication between different synchronous modules on a bus. We explore issues related to validation, module interfaces and tool flows, while looking at advantages in power savings, timing closure and Time-to-Market/Time-to-Money (TTM). Our exploration vehicle is the IntelregPXA27x Peripheral Bus (PB) - a common interface for connecting peripherals on PXA27x and related processor families in Intel's cellular and handheld application and communication domain.
{"title":"Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus","authors":"Andrew M. Scott, M. Schuelein, M. Roncken, Jin-Jer Hwan, J. Bainbridge, John Mawer, D. L. Jackson, A. Bardsley","doi":"10.1109/ASYNC.2007.11","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.11","url":null,"abstract":"For today's SoC designer, on-die variation, clock distribution, timing closure, and power concerns confront the desire to get products to market quicker. Each new process generation makes the challenge greater as process skews, complexity, and frequency become more onerous. This is particularly true for signals that have to travel across larger portions of a chip such as clocks and buses. In this paper, we examine the use of GALS (Globally Asynchronous, Locally Synchronous) [Chapiro, 1985] techniques to address on-chip communication between different synchronous modules on a bus. We explore issues related to validation, module interfaces and tool flows, while looking at advantages in power savings, timing closure and Time-to-Market/Time-to-Money (TTM). Our exploration vehicle is the IntelregPXA27x Peripheral Bus (PB) - a common interface for connecting peripherals on PXA27x and related processor families in Intel's cellular and handheld application and communication domain.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126022592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. D'Alessandro, A. Mokhov, A. Bystrov, A. Yakovlev
Designs which require a phase relationship between two signals to be maintained along a link benefit from the use of repeaters which actively regenerate this relationship. This paper discusses some implementations of phase-regeneration circuits and attempts to introduce the reader to the issues encountered in the design of such circuitry. The paper proposes various design solutions for the dual-rail case, extending the work to the multiple-rail case. A novel device which is able to reconstruct a sequence of events is also presented, the transition sequence encoder. Simulation results are provided with discussion on the relative performance.
{"title":"Delay/Phase Regeneration Circuits","authors":"C. D'Alessandro, A. Mokhov, A. Bystrov, A. Yakovlev","doi":"10.1109/ASYNC.2007.14","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.14","url":null,"abstract":"Designs which require a phase relationship between two signals to be maintained along a link benefit from the use of repeaters which actively regenerate this relationship. This paper discusses some implementations of phase-regeneration circuits and attempts to introduce the reader to the issues encountered in the design of such circuitry. The paper proposes various design solutions for the dual-rail case, extending the work to the multiple-rail case. A novel device which is able to reconstruct a sequence of events is also presented, the transition sequence encoder. Simulation results are provided with discussion on the relative performance.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124121356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tiberiu Chelcea, Girish Venkataramani, S. Goldstein
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous tool flows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.
{"title":"Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis","authors":"Tiberiu Chelcea, Girish Venkataramani, S. Goldstein","doi":"10.1109/ASYNC.2007.10","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.10","url":null,"abstract":"Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous tool flows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124400281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchronous FIFO rings. A traditional PRBS generator using a linear feedback shift register (LFSR) can only generate a single maximal-length pattern with a fixed period. Our proposed FIFO implementation allows a single circuit to produce many different patterns of different periods, all of which are maximal-length, based on the initialization of the circuit. It also provides intrinsic fine-grain pipelining which alleviates the large feedback logic overhead in configurations with many taps, making such implementations practical. With an asynchronous-to-clocked interface, one can use the circuit in a synchronous environment. Detailed simulation results are presented.
{"title":"A Configurable Asynchronous Pseudorandom Bit Sequence Generator","authors":"A. Chow, William S. Coates, D. Hopkins","doi":"10.1109/ASYNC.2007.5","DOIUrl":"https://doi.org/10.1109/ASYNC.2007.5","url":null,"abstract":"We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchronous FIFO rings. A traditional PRBS generator using a linear feedback shift register (LFSR) can only generate a single maximal-length pattern with a fixed period. Our proposed FIFO implementation allows a single circuit to produce many different patterns of different periods, all of which are maximal-length, based on the initialization of the circuit. It also provides intrinsic fine-grain pipelining which alleviates the large feedback logic overhead in configurations with many taps, making such implementations practical. With an asynchronous-to-clocked interface, one can use the circuit in a synchronous environment. Detailed simulation results are presented.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"11 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113985422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dr. Sequin has been a CAD tool builder for the last 30 years. He has participated in the design of solid-state filters and image sensors, institutional research buildings, mechanical toys, and, more recently, abstract geometrical sculptures.
{"title":"Thinking Outside the Box in Geometry and Art","authors":"C. Séquin","doi":"10.1109/async.2007.29","DOIUrl":"https://doi.org/10.1109/async.2007.29","url":null,"abstract":"Dr. Sequin has been a CAD tool builder for the last 30 years. He has participated in the design of solid-state filters and image sensors, institutional research buildings, mechanical toys, and, more recently, abstract geometrical sculptures.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Robots not only can be useful, but also can entertain. From the robot fountains at Bellagio to humanoid figures and Jurassic park dinosaurs, Sarcos has applied new technology to make things move in complex and entertaining ways. Major improvements in the cost and reliability of sensors and actuators have made these projects possible; improvements that also apply to more practical work in robots for demanding and dangerous tasks. Along the way we've learned much about the behavior of people interacting with robots - our engineers, our artists, our clients and their audiences.
{"title":"Too Many Robots, Too Little Time","authors":"","doi":"10.1109/async.2007.30","DOIUrl":"https://doi.org/10.1109/async.2007.30","url":null,"abstract":"Robots not only can be useful, but also can entertain. From the robot fountains at Bellagio to humanoid figures and Jurassic park dinosaurs, Sarcos has applied new technology to make things move in complex and entertaining ways. Major improvements in the cost and reliability of sensors and actuators have made these projects possible; improvements that also apply to more practical work in robots for demanding and dangerous tasks. Along the way we've learned much about the behavior of people interacting with robots - our engineers, our artists, our clients and their audiences.","PeriodicalId":136595,"journal":{"name":"13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133196969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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