System-level design of embedded computer systems is essential to manage complexity and enhance designer productivity. Viewing designs at different abstraction levels allows developers to evaluate the system performance early in the design cycle. System-level design languages (SLDLs) allow the representation of a system at multiple levels of abstraction. Two leading SLDLs, SpecC and SystemC, are taught in Iowa State University's graduate-level embedded systems course, CPRE 588. SpecC includes a handful of explicit language constructs that directly address characteristics of embedded applications, which gives students a quick start into understanding the concepts of system-level design. Moreover, a clear refinement methodology is defined for SpecC. However, SystemC has widespread industry support in many commercial tools, which gives students experience with actual practices. In this paper, we describe our strategy of teaching both SpecC and SystemC so as to leverage the strengths of both languages and provide a balance of theory and practice.
{"title":"Teaching system-level design using SpecC and SystemC","authors":"Robert D. Walstrom, J. Schneider, D. Rover","doi":"10.1109/MSE.2005.59","DOIUrl":"https://doi.org/10.1109/MSE.2005.59","url":null,"abstract":"System-level design of embedded computer systems is essential to manage complexity and enhance designer productivity. Viewing designs at different abstraction levels allows developers to evaluate the system performance early in the design cycle. System-level design languages (SLDLs) allow the representation of a system at multiple levels of abstraction. Two leading SLDLs, SpecC and SystemC, are taught in Iowa State University's graduate-level embedded systems course, CPRE 588. SpecC includes a handful of explicit language constructs that directly address characteristics of embedded applications, which gives students a quick start into understanding the concepts of system-level design. Moreover, a clear refinement methodology is defined for SpecC. However, SystemC has widespread industry support in many commercial tools, which gives students experience with actual practices. In this paper, we describe our strategy of teaching both SpecC and SystemC so as to leverage the strengths of both languages and provide a balance of theory and practice.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122297536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diego Fernando Jimenez Orostegui, L. Indrusiak, M. Glesner
Education in microelectronics technology ideally reaches beyond theoretical lecturing. After basic information is reviewed, practical activities allow for clarification of learned concepts. Therefore, e-learning environments in microelectronics must allow for such activities. This is not easy to accomplish due to the fact that practical experience is, for most students, available only inside shared laboratory rooms. The objective of the present project is to address this problem by granting remote access of reconfigurable hardware to students. Using this concept, students can reach real reconfigurable hardware as a part of a model within a simulation tool, in this case Ptolemy II. They can upload their own or use existing configurations to the hardware, and then make it interact with other Actors of the simulation. Such a tool enhances e-learning systems where the students can also access design automation tools, libraries, and prototyping platforms. Moreover, through these systems, students can communicate with fellow students and instructors.
{"title":"Proxy-based integration of reconfigurable hardware within simulation environments: improving e-learning experience in microelectronics","authors":"Diego Fernando Jimenez Orostegui, L. Indrusiak, M. Glesner","doi":"10.1109/MSE.2005.45","DOIUrl":"https://doi.org/10.1109/MSE.2005.45","url":null,"abstract":"Education in microelectronics technology ideally reaches beyond theoretical lecturing. After basic information is reviewed, practical activities allow for clarification of learned concepts. Therefore, e-learning environments in microelectronics must allow for such activities. This is not easy to accomplish due to the fact that practical experience is, for most students, available only inside shared laboratory rooms. The objective of the present project is to address this problem by granting remote access of reconfigurable hardware to students. Using this concept, students can reach real reconfigurable hardware as a part of a model within a simulation tool, in this case Ptolemy II. They can upload their own or use existing configurations to the hardware, and then make it interact with other Actors of the simulation. Such a tool enhances e-learning systems where the students can also access design automation tools, libraries, and prototyping platforms. Moreover, through these systems, students can communicate with fellow students and instructors.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122771846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jean-Francois Thibeault, M. Hubin, F. Deslauriers, P. Samson, G. Bois
This paper describes a mine controller project used as laboratory material by undergraduate students for the "Real-Time Systems" course. This mine controller runs on a real-time operating system communicating with dedicated hardware. The complete embedded system is implemented on the AMIRIX AP100 FPGA development board.
{"title":"A reprogrammable SoC design for a real-time control application","authors":"Jean-Francois Thibeault, M. Hubin, F. Deslauriers, P. Samson, G. Bois","doi":"10.1109/MSE.2005.11","DOIUrl":"https://doi.org/10.1109/MSE.2005.11","url":null,"abstract":"This paper describes a mine controller project used as laboratory material by undergraduate students for the \"Real-Time Systems\" course. This mine controller runs on a real-time operating system communicating with dedicated hardware. The complete embedded system is implemented on the AMIRIX AP100 FPGA development board.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117333350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jean-Samuel Chenard, Ahmed Usman Khalid, M. Prokić, Rong Zhang, K. Lim, A. Chattopadhyay, Z. Zilic
We present the design and use of the McGumps laboratory kit for teaching microprocessor and embedded systems. The kit facilitates efficient learning of relevant hardware and software design techniques that will not get outdated soon. We describe the typical use of this kit in our courses.
{"title":"Expandable and robust laboratory for microprocessor systems","authors":"Jean-Samuel Chenard, Ahmed Usman Khalid, M. Prokić, Rong Zhang, K. Lim, A. Chattopadhyay, Z. Zilic","doi":"10.1109/MSE.2005.29","DOIUrl":"https://doi.org/10.1109/MSE.2005.29","url":null,"abstract":"We present the design and use of the McGumps laboratory kit for teaching microprocessor and embedded systems. The kit facilitates efficient learning of relevant hardware and software design techniques that will not get outdated soon. We describe the typical use of this kit in our courses.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121475132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Stine, J. Grad, I. D. Castellanos, Jeff M. Blank, V. Dave, M. Prakash, N. Iliev, N. Jachimiec
A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended for use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in system on chip design through the MOSIS educational program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.
{"title":"A framework for high-level synthesis of system on chip designs","authors":"J. Stine, J. Grad, I. D. Castellanos, Jeff M. Blank, V. Dave, M. Prakash, N. Iliev, N. Jachimiec","doi":"10.1109/MSE.2005.8","DOIUrl":"https://doi.org/10.1109/MSE.2005.8","url":null,"abstract":"A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended for use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in system on chip design through the MOSIS educational program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133614701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Oliver, F. Haim, S. Fernandez, Javier Rodriguez, P. Rolando
This paper describes a new logic design course implementation in 2004. In the new course the labs and the evaluation methods were changed. In the old course the labs were developed in a traditional manner in the school lab rooms; and in the present system the lab assignments were done in the student's home with a new designed PLD board, and then presented and evaluated by the teachers. The boards were successfully designed, and a great number of these hardware kits were assembled and distributed to the groups of students for the whole semester. The goals were fulfilled with good acceptance from the students and many advantages from an educational point of view.
{"title":"Hardware lab at home possible with ultra low cost boards [logic design course]","authors":"J. Oliver, F. Haim, S. Fernandez, Javier Rodriguez, P. Rolando","doi":"10.1109/MSE.2005.33","DOIUrl":"https://doi.org/10.1109/MSE.2005.33","url":null,"abstract":"This paper describes a new logic design course implementation in 2004. In the new course the labs and the evaluation methods were changed. In the old course the labs were developed in a traditional manner in the school lab rooms; and in the present system the lab assignments were done in the student's home with a new designed PLD board, and then presented and evaluated by the teachers. The boards were successfully designed, and a great number of these hardware kits were assembled and distributed to the groups of students for the whole semester. The goals were fulfilled with good acceptance from the students and many advantages from an educational point of view.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"2003 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125784717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
What comes after most state-of-the-art semiconductor fabs are moved to Asia? Would this trend fundamentally change the educational needs of students in the U.S. majoring in electrical engineering (E.E.)? This paper lists several major challenges for educating future RF/analog integrated circuit (IC) designers in the U.S in light of this "outsourcing" trend. The outline of a 3-quarter graduate-level RF/analog IC design series (ECE265ABC) that the author has been privileged to teach at UC San Diego (UCSD) is discussed to address some of those specific challenges.
{"title":"What comes after most semiconductor fabs are \"outsourced\" to Asia? Major challenges in educating future RF/analog IC designers in the U.S","authors":"D. Lie","doi":"10.1109/MSE.2005.65","DOIUrl":"https://doi.org/10.1109/MSE.2005.65","url":null,"abstract":"What comes after most state-of-the-art semiconductor fabs are moved to Asia? Would this trend fundamentally change the educational needs of students in the U.S. majoring in electrical engineering (E.E.)? This paper lists several major challenges for educating future RF/analog integrated circuit (IC) designers in the U.S in light of this \"outsourcing\" trend. The outline of a 3-quarter graduate-level RF/analog IC design series (ECE265ABC) that the author has been privileged to teach at UC San Diego (UCSD) is discussed to address some of those specific challenges.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127838850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Pleskacz, T. Borejko, T. Gugala, P. Pizon, V. Stopjaková
The educational integrated circuit, DefSim, is described. This chip is dedicated to the development of students' skills in fault simulation and test pattern generation for digital circuits. It allows applying both voltage and current test methods and offers comparing of their efficiencies on basic digital circuit examples. DefSim was manufactured and its operation was verified experimentally.
{"title":"DefSim - the educational integrated circuit for defect simulation","authors":"W. Pleskacz, T. Borejko, T. Gugala, P. Pizon, V. Stopjaková","doi":"10.1109/MSE.2005.24","DOIUrl":"https://doi.org/10.1109/MSE.2005.24","url":null,"abstract":"The educational integrated circuit, DefSim, is described. This chip is dedicated to the development of students' skills in fault simulation and test pattern generation for digital circuits. It allows applying both voltage and current test methods and offers comparing of their efficiencies on basic digital circuit examples. DefSim was manufactured and its operation was verified experimentally.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a manual that covers the necessary design steps for a basic ASIC design flow. It is shown how the manual writing process is organized such that each chapter covers a certain step in the design flow. The manual has been written especially with practicality in mind and has been successfully applied to undergraduate and postgraduate teaching.
{"title":"A manual on ASIC front to back end design flow","authors":"J. Rodrigues, M. Kamuf, H. Hedberg, V. Öwall","doi":"10.1109/MSE.2005.9","DOIUrl":"https://doi.org/10.1109/MSE.2005.9","url":null,"abstract":"This paper presents a manual that covers the necessary design steps for a basic ASIC design flow. It is shown how the manual writing process is organized such that each chapter covers a certain step in the design flow. The manual has been written especially with practicality in mind and has been successfully applied to undergraduate and postgraduate teaching.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133616869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we describe an analog leaf cell (ALC) that was created to facilitate teaching analog circuit design to senior/graduate EE. It is intended as a teaching tool to introduce the student to the design, fabrication and test cycle in a simple yet complete manner. The ALC is a sea-of-gates semi-custom IC design approach that reduces design and fabrication time.
{"title":"An analog leaf cell for analog circuit design","authors":"D. Parent, E. Basham, S. Ng, P. Weil","doi":"10.1109/MSE.2005.17","DOIUrl":"https://doi.org/10.1109/MSE.2005.17","url":null,"abstract":"In this paper, we describe an analog leaf cell (ALC) that was created to facilitate teaching analog circuit design to senior/graduate EE. It is intended as a teaching tool to introduce the student to the design, fabrication and test cycle in a simple yet complete manner. The ALC is a sea-of-gates semi-custom IC design approach that reduces design and fabrication time.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133820729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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