T. Silva, J. Vortmann, L. Agostini, A. Susin, S. Bampi
This paper presents a low cost and memoryless hardware design for the Context Adaptive Variable Length Decoder (CAVLD) of the H.264/AVC video coding standard. Usually, a large number of memory bits and memory accesses are required to decode the CAVLD symbols in H.264/AVC since a great number of syntax elements are decoded based on look-up tables. This is an important problem given the high hardware cost and the high power dissipation caused by the large number of memory accesses. Thus, to solve this problem, we designed an efficient decoding of syntax elements using tree structures. The architecture designed was described in VHDL and synthesized to Altera Stratix II FPGA and to TSMC 0.18μm standard-cells technologies. The results obtained show that our architecture has significant savings in hardware resources consumption and in the number of memory accesses in comparison to other published works. Our design reached the necessary throughput to decode SDTV videos (720x576 pixels) in real-time.
针对H.264/AVC视频编码标准中的上下文自适应变长解码器(CAVLD)，提出了一种低成本、无内存的硬件设计方案。在H.264/AVC中，由于大量的语法元素是基于查找表解码的，因此通常需要大量的内存位和内存访问来解码CAVLD符号。考虑到高硬件成本和大量内存访问导致的高功耗，这是一个重要的问题。因此，为了解决这个问题，我们设计了一个使用树结构的语法元素的有效解码。采用VHDL语言描述了设计的结构，并将其合成为Altera Stratix II FPGA和TSMC 0.18μm标准单元技术。结果表明，与其他已发表的作品相比，我们的架构在硬件资源消耗和内存访问次数方面有显着的节省。我们的设计达到了实时解码SDTV视频(720x576像素)所需的吞吐量。
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