Vyas Venkataraman, Di Wang, A. Mahram, W. Qin, Mrinal Bose, J. Bhadra
Due to the large semantic gap between transaction level models and actual implementations, hardware synthesis based on system level models has been a great challenge. Aiming to close the semantic gap, we studied an approach that uses rendezvous to model communication. By allowing both conjunctive and disjunctive composition of rendezvous, the approach supports flexible communication patterns involving multiple processes. However, a practical issue of the model is the complexity of scheduling of multiparty rendezvous, which is NP hard in general. This paper proposes an efficient scheduling algorithm. It begins by encapsulating state transition information of processes into a relation graph. It then creates a tree that relates edge combinations. The tree is used to guide the scheduler at run time to search for schedulable sets. Experimental results prove that this algorithm improves our scheduler significantly. The algorithm lays the ground for the synthesis of the communication and synchronization circuitry for the system.
{"title":"Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models","authors":"Vyas Venkataraman, Di Wang, A. Mahram, W. Qin, Mrinal Bose, J. Bhadra","doi":"10.1109/ISVLSI.2009.8","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.8","url":null,"abstract":"Due to the large semantic gap between transaction level models and actual implementations, hardware synthesis based on system level models has been a great challenge. Aiming to close the semantic gap, we studied an approach that uses rendezvous to model communication. By allowing both conjunctive and disjunctive composition of rendezvous, the approach supports flexible communication patterns involving multiple processes. However, a practical issue of the model is the complexity of scheduling of multiparty rendezvous, which is NP hard in general. This paper proposes an efficient scheduling algorithm. It begins by encapsulating state transition information of processes into a relation graph. It then creates a tree that relates edge combinations. The tree is used to guide the scheduler at run time to search for schedulable sets. Experimental results prove that this algorithm improves our scheduler significantly. The algorithm lays the ground for the synthesis of the communication and synchronization circuitry for the system.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134196295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Pecar, M. Janež, N. Zimic, M. Mraz, I. L. Bajec
Quantum-dot Cellular Automata (QCA) were demonstrated to be a possible candidate for the implementation of a future multi-valued processing platform. Recent papers show that the introduction of adiabatic switching and the elegant application of the adiabatic pipelining concept in the QCA logic design can be used to efficiently solve the issues of the elementary ternary QCA logic primitives. The architectures of the resulting ternary QCAs become similar to their binary counterparts and thus the design rules for large circuit design remain similar to those developed for the binary QCA domain. In spite of this the design of the binary QCA SR memorizing cell cannot be directly transferred to the ternary domain, mostly because the control logic cannot properly handle the third value. We here propose a ternary QCA memorizing cell that efficiently exploits the pipelining mechanism at a wire level. It is centered on the circulating memory model (i.e. the memory in motion concept), which proved to be an efficient concept in memorizing cell design in the binary QCA domain. The proposed memorizing cell is capable of serving as one trit (ternary digit) of memory and represents a step forward to the ternary register, one of the basic building blocks of a ternary processor.
{"title":"The Ternary Quantum-dot Cellular Automata Memorizing Cell","authors":"P. Pecar, M. Janež, N. Zimic, M. Mraz, I. L. Bajec","doi":"10.1109/ISVLSI.2009.32","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.32","url":null,"abstract":"Quantum-dot Cellular Automata (QCA) were demonstrated to be a possible candidate for the implementation of a future multi-valued processing platform. Recent papers show that the introduction of adiabatic switching and the elegant application of the adiabatic pipelining concept in the QCA logic design can be used to efficiently solve the issues of the elementary ternary QCA logic primitives. The architectures of the resulting ternary QCAs become similar to their binary counterparts and thus the design rules for large circuit design remain similar to those developed for the binary QCA domain. In spite of this the design of the binary QCA SR memorizing cell cannot be directly transferred to the ternary domain, mostly because the control logic cannot properly handle the third value. We here propose a ternary QCA memorizing cell that efficiently exploits the pipelining mechanism at a wire level. It is centered on the circulating memory model (i.e. the memory in motion concept), which proved to be an efficient concept in memorizing cell design in the binary QCA domain. The proposed memorizing cell is capable of serving as one trit (ternary digit) of memory and represents a step forward to the ternary register, one of the basic building blocks of a ternary processor.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116707743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a novel low phase-noise and wide tuning-range CMOS differential Voltage-Controlled Oscillator (VCO) for a frequency ΔΣ modulator (FDSM) is presented. The VCO which converts an analog input voltage to phase information is based on a differential ring oscillator with modified symmetric load and a positive feedback in the differential delay cells, combined with a new bias circuit. The proposed VCO with two stages operating at a low power supply voltage of 0.6V can achieve low power consumption of 212uW, and wide tuning-range by increasing the operating frequency range by about 22%. The phase noise is -132dBc/Hz at 600KHz offset from the centre frequency of 480MHz. The new VCO has a good linearity reducing harmonic distortion in the ΔΣ modulator. The circuits are designed using a 65nm CMOS process.
{"title":"Low Phase-Noise and Wide Tuning-Range CMOS Differential VCO for Frequency ?S Modulator","authors":"T. Cao, D. Wisland, T. Lande, F. Moradi","doi":"10.1109/ISVLSI.2009.36","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.36","url":null,"abstract":"In this paper, a novel low phase-noise and wide tuning-range CMOS differential Voltage-Controlled Oscillator (VCO) for a frequency ΔΣ modulator (FDSM) is presented. The VCO which converts an analog input voltage to phase information is based on a differential ring oscillator with modified symmetric load and a positive feedback in the differential delay cells, combined with a new bias circuit. The proposed VCO with two stages operating at a low power supply voltage of 0.6V can achieve low power consumption of 212uW, and wide tuning-range by increasing the operating frequency range by about 22%. The phase noise is -132dBc/Hz at 600KHz offset from the centre frequency of 480MHz. The new VCO has a good linearity reducing harmonic distortion in the ΔΣ modulator. The circuits are designed using a 65nm CMOS process.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123663826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, B. Ravi
With shift towards heterogeneous core architectures imminent, the uniform grid based ground plane model that is currently employed for chip-multiprocessors will no longer suf¿ce. It is practically impossible to achieve absolute zero potential at all grid nodes of the uniform ground plane model with advent of heterogeneous cores. Differential injection of current into the ground plane by different heterogeneous core partitions results in voltage gradients across the ground plane, which is detrimental to the operation of the processor. The extremely stochastic spiking activity of different cores further accentuates the problem. To overcome the problem of varying voltage distribution across the ground plane, we propose a ¿rst-ever ground plane model structured as a non-uniform RLC interconnect grid. A simulated annealing optimization is employed with parameter of ‘temperature’ as each node in the grid and impedance as the cost function ’δe’ to arrive at the non-uniform grid structure.
{"title":"A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient","authors":"N. Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, B. Ravi","doi":"10.1109/ISVLSI.2009.52","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.52","url":null,"abstract":"With shift towards heterogeneous core architectures imminent, the uniform grid based ground plane model that is currently employed for chip-multiprocessors will no longer suf¿ce. It is practically impossible to achieve absolute zero potential at all grid nodes of the uniform ground plane model with advent of heterogeneous cores. Differential injection of current into the ground plane by different heterogeneous core partitions results in voltage gradients across the ground plane, which is detrimental to the operation of the processor. The extremely stochastic spiking activity of different cores further accentuates the problem. To overcome the problem of varying voltage distribution across the ground plane, we propose a ¿rst-ever ground plane model structured as a non-uniform RLC interconnect grid. A simulated annealing optimization is employed with parameter of ‘temperature’ as each node in the grid and impedance as the cost function ’δe’ to arrive at the non-uniform grid structure.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"51 Pt 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126237819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.
{"title":"Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate","authors":"H. Thapliyal, N. Ranganathan","doi":"10.1109/ISVLSI.2009.49","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.49","url":null,"abstract":"Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125797203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Future microprocessors are expected to observe higher transient error rates in combinational logic due to technology scaling and dense integration. We propose a simple transient error protection mechanism for embedded systems exploiting frequent small operand values of instructions and frequently used shift operations. The conditions for applicable instructions for the proposed mechanism are explored, which account for 84% of total instructions executed on average. The operands of these instructions are replicated in ALU directly and other instructions are protected using time-redundant double execution. Our experimental results show that the proposed mechanism incurs 12% performance hit and 4% energy hit, on average, with a low impact on the chip area (7% of the execution unit area).
{"title":"TEPS: Transient Error Protection Utilizing Sub-word Parallelism","authors":"Seokin Hong, Soontae Kim","doi":"10.1109/ISVLSI.2009.21","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.21","url":null,"abstract":"Future microprocessors are expected to observe higher transient error rates in combinational logic due to technology scaling and dense integration. We propose a simple transient error protection mechanism for embedded systems exploiting frequent small operand values of instructions and frequently used shift operations. The conditions for applicable instructions for the proposed mechanism are explored, which account for 84% of total instructions executed on average. The operands of these instructions are replicated in ALU directly and other instructions are protected using time-redundant double execution. Our experimental results show that the proposed mechanism incurs 12% performance hit and 4% energy hit, on average, with a low impact on the chip area (7% of the execution unit area).","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129581210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as basic operations. Hence, improving the additions characteristics will improve the performance of almost all arithmetic modules. Several HRSD adders have been introduced in literatures. In this paper a new maximally redundant HRSD adder is proposed. This adder is compared to some most efficient HRSD adders previously published. The proposed adder is fabricated using a standard TSMC 65nm CMOS technology at 1volt supply voltage. The adder consumes 2.5% less power than the best previous published HRSD design. These implementations are also synthesized with FPGA flow on Xilinx Virtex2. The experimental result shows 5% and 6% decreases in the area and delay, respectively.
{"title":"Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation","authors":"S. Timarchi, K. Navi, O. Kavehei","doi":"10.1109/ISVLSI.2009.30","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.30","url":null,"abstract":"Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as basic operations. Hence, improving the additions characteristics will improve the performance of almost all arithmetic modules. Several HRSD adders have been introduced in literatures. In this paper a new maximally redundant HRSD adder is proposed. This adder is compared to some most efficient HRSD adders previously published. The proposed adder is fabricated using a standard TSMC 65nm CMOS technology at 1volt supply voltage. The adder consumes 2.5% less power than the best previous published HRSD design. These implementations are also synthesized with FPGA flow on Xilinx Virtex2. The experimental result shows 5% and 6% decreases in the area and delay, respectively.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116550178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reducing off-chip bus power consumption has become one of the key issues for low power system design. Although methods have been proposed to reduce the power dissipated in parallel buses, these techniques do not apply to serial communication since they work on consecutive data words. The data line in synchronous serial communication is a major source of power dissipation, apart from the clock line. The clock line cannot be modified due to the requirements of data recovery. This work outlines a novel transition inversion based data coding protocol by which these transitions on the data line can be reduced for synchronous serial buses like JTAG, SPI, I2C etc. Simulation results show up to 31.9% reduction in transitions, with negligible performance loss. Analysis on the utility of the proposed technique for error detection shows that the technique can be used instead of the parity bit technique since both are found to have the same average error detection capability.
{"title":"Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication","authors":"A. Ramachandran, Bharghava Rajaram, M. Srinivas","doi":"10.1109/ISVLSI.2009.43","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.43","url":null,"abstract":"Reducing off-chip bus power consumption has become one of the key issues for low power system design. Although methods have been proposed to reduce the power dissipated in parallel buses, these techniques do not apply to serial communication since they work on consecutive data words. The data line in synchronous serial communication is a major source of power dissipation, apart from the clock line. The clock line cannot be modified due to the requirements of data recovery. This work outlines a novel transition inversion based data coding protocol by which these transitions on the data line can be reduced for synchronous serial buses like JTAG, SPI, I2C etc. Simulation results show up to 31.9% reduction in transitions, with negligible performance loss. Analysis on the utility of the proposed technique for error detection shows that the technique can be used instead of the parity bit technique since both are found to have the same average error detection capability.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131565101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anshul Singh, Aman Gupta, S. Veeramachaneni, M. Srinivas
Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.
{"title":"A High Performance Unified BCD and Binary Adder/Subtractor","authors":"Anshul Singh, Aman Gupta, S. Veeramachaneni, M. Srinivas","doi":"10.1109/ISVLSI.2009.40","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.40","url":null,"abstract":"Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132310324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has a power overhead and PDP overhead of 1.7X and 2.8X, respectively, much higher than that of the transmission-gate master-slave flip flop(TG-MSFF) . The TG-MSFF exhibits the lowest relative power and PDP overheads of 30.87% and 9% ,respectively.
{"title":"Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits","authors":"H. Mostafa, M. Anis, M. Elmasry","doi":"10.1109/ISVLSI.2009.23","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.23","url":null,"abstract":"In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has a power overhead and PDP overhead of 1.7X and 2.8X, respectively, much higher than that of the transmission-gate master-slave flip flop(TG-MSFF) . The TG-MSFF exhibits the lowest relative power and PDP overheads of 30.87% and 9% ,respectively.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117270956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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