To the members of SigMicro: I have been asked by the Newsletter Editor, Vicki Allan, if I wanted to comment on Micro 21. I guess I'd much rather hear what others have to say. On the other hand, I do want to report that it was a privilege to take my turn as your Workshop Chairman, and I wish Gerry and others success in the years ahead with Micro n, as we continue to increase n. As I did at the Workshop itself, I want to again express my thanks to Rich Belgard and Wen-mei Hwu for taking on such a large part of the job. In the case of Rich, it was yet another Micro n that he put his own personal good stamp on. In the case of Wen-mei, it was the kind of thorough first rate job that I have become used to seeing him do. I eagerly look forward to the Micro n Workshop that we convince him to lead as General Chairman. For those of you concerned about such things, we made a bunch of money, enough to subsidize mailing the Proceedings to the SigMI-CRO membership and still report a substantial profit to our co-sponsors, IEEE and ACM. Now, we look forward to Micro 22. Gerry Johnson has carved out an exciting first for us in organizing it in Dublin. The interest in Microprogramming and Microarchitecture in general and the quality of the technical interaction at the Workshop in particular continue to grow. In addition, the wonder of the country , from Galway to Donegal to the Antrim coast, is not to be missed. So, for both professional technical reasons and for personal enrichment reasons, I encourage you to plan on spending part of August in Dublin at Micro 22. Finally, I would urge the subsequent Workshop Chairmen to keep in mind the sentiment of the attendees at Micro 21, as expressed in our much-too-long meeting on Thursday night of the Workshop , that we wish to continue the co-sponsorship of the workshop by both professional societies (IEEE and ACM). As was pointed out so eloquently by me, each society contributes to our professional needs in different and complementary ways, and we are fortunate to be able to enjoy both and not have to choose between the two.
{"title":"Micro-21 from the chair","authors":"Y. Patt","doi":"10.1145/378818.378847","DOIUrl":"https://doi.org/10.1145/378818.378847","url":null,"abstract":"To the members of SigMicro: I have been asked by the Newsletter Editor, Vicki Allan, if I wanted to comment on Micro 21. I guess I'd much rather hear what others have to say. On the other hand, I do want to report that it was a privilege to take my turn as your Workshop Chairman, and I wish Gerry and others success in the years ahead with Micro n, as we continue to increase n. As I did at the Workshop itself, I want to again express my thanks to Rich Belgard and Wen-mei Hwu for taking on such a large part of the job. In the case of Rich, it was yet another Micro n that he put his own personal good stamp on. In the case of Wen-mei, it was the kind of thorough first rate job that I have become used to seeing him do. I eagerly look forward to the Micro n Workshop that we convince him to lead as General Chairman. For those of you concerned about such things, we made a bunch of money, enough to subsidize mailing the Proceedings to the SigMI-CRO membership and still report a substantial profit to our co-sponsors, IEEE and ACM. Now, we look forward to Micro 22. Gerry Johnson has carved out an exciting first for us in organizing it in Dublin. The interest in Microprogramming and Microarchitecture in general and the quality of the technical interaction at the Workshop in particular continue to grow. In addition, the wonder of the country , from Galway to Donegal to the Antrim coast, is not to be missed. So, for both professional technical reasons and for personal enrichment reasons, I encourage you to plan on spending part of August in Dublin at Micro 22. Finally, I would urge the subsequent Workshop Chairmen to keep in mind the sentiment of the attendees at Micro 21, as expressed in our much-too-long meeting on Thursday night of the Workshop , that we wish to continue the co-sponsorship of the workshop by both professional societies (IEEE and ACM). As was pointed out so eloquently by me, each society contributes to our professional needs in different and complementary ways, and we are fortunate to be able to enjoy both and not have to choose between the two.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"288 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132119659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The instruction queue is a critical component of the proposed mlcroarchitecture where executable instructions are detected and delivered to the execution unit. This paper clarifies the issue of loading instructions into the instruction queue and evaluates the resulting performance due to different schemes. paths are identified in the complicated UNIX programs so that trace scheduling can be effectively applied. Experimental results are provided for ten UNIX system and CAD programs which all exhibit complicated control structure. This is the first paper to address the issue of applying trace scheduling to complicated programs. The work is critical to adapting trace scheduling to RISC's and other upcoming pipelined, parallel mlcroarchltectures. Research The CMOS 370 has some Control Store on chip and some off. A small on-chip Control Store holds the first two microwords of each microsequence (target of conditional branches). A close look reveals that the two-level Control Store structure can be viewed as a programmer managed target instruction buffer. This structure makes it possible to access one microinstruction from a (mostly off-chip) large Control store every cycle while achieving a short cycle time. Efficient trapping is proposed to support efficient instruction emulation in processors with hardwired control. This makes the issue of instruction set design relatively independent of the implementation (hardwired or microprogrammed). • "Multiple Instruction Issue and Single-Chip Processors," A. Pleszkun and G. Sohi, U. of Wisconsin-Madison. Sometimes issuing multiple instructions is not a win. It would be interesting to experiment on the effect of compilation support (trace scheduling, register allocation, etc.) on the instruction issue rate. Comparing the results presented in this paper and those presented by the VLIW team, compilation support seems to be critical for issuing multiple instructions per cycle. The paper discusses the dilemma due to the interdependence between data routing and code scheduling in ASIC code generation. This issue corresponds closely to the one regarding the code scheduling and register allocation for pipelined and/or wide instruction architectures. The trend is to consider both factors together during code generation. The dynamic reconfigurability is a very interesting feature of the proposed ASIC paradigm. However, the slow prototype makes one wonder if a simple microprocessor can be programmed to achieve the same performance for the target applications. • "Implementing a Prolog Machine with Multiple Functional Units," A. Singhal and Y. Patt, U. C. Berkeley. Parallel unification and execution result in factor of 4 speedup over the Berkeley PLM. …
{"title":"Micro-21 from the program chair","authors":"Wen-mei W. Hwu","doi":"10.1145/378818.378848","DOIUrl":"https://doi.org/10.1145/378818.378848","url":null,"abstract":"The instruction queue is a critical component of the proposed mlcroarchitecture where executable instructions are detected and delivered to the execution unit. This paper clarifies the issue of loading instructions into the instruction queue and evaluates the resulting performance due to different schemes. paths are identified in the complicated UNIX programs so that trace scheduling can be effectively applied. Experimental results are provided for ten UNIX system and CAD programs which all exhibit complicated control structure. This is the first paper to address the issue of applying trace scheduling to complicated programs. The work is critical to adapting trace scheduling to RISC's and other upcoming pipelined, parallel mlcroarchltectures. Research The CMOS 370 has some Control Store on chip and some off. A small on-chip Control Store holds the first two microwords of each microsequence (target of conditional branches). A close look reveals that the two-level Control Store structure can be viewed as a programmer managed target instruction buffer. This structure makes it possible to access one microinstruction from a (mostly off-chip) large Control store every cycle while achieving a short cycle time. Efficient trapping is proposed to support efficient instruction emulation in processors with hardwired control. This makes the issue of instruction set design relatively independent of the implementation (hardwired or microprogrammed). • \"Multiple Instruction Issue and Single-Chip Processors,\" A. Pleszkun and G. Sohi, U. of Wisconsin-Madison. Sometimes issuing multiple instructions is not a win. It would be interesting to experiment on the effect of compilation support (trace scheduling, register allocation, etc.) on the instruction issue rate. Comparing the results presented in this paper and those presented by the VLIW team, compilation support seems to be critical for issuing multiple instructions per cycle. The paper discusses the dilemma due to the interdependence between data routing and code scheduling in ASIC code generation. This issue corresponds closely to the one regarding the code scheduling and register allocation for pipelined and/or wide instruction architectures. The trend is to consider both factors together during code generation. The dynamic reconfigurability is a very interesting feature of the proposed ASIC paradigm. However, the slow prototype makes one wonder if a simple microprocessor can be programmed to achieve the same performance for the target applications. • \"Implementing a Prolog Machine with Multiple Functional Units,\" A. Singhal and Y. Patt, U. C. Berkeley. Parallel unification and execution result in factor of 4 speedup over the Berkeley PLM. …","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121297006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to have a broad range of performance in processors, more than one model must exist. A family of processors infers systems with enough commonality that a smaller model can be upgraded to a larger one with minimum effort by retaining as much of the existing hardware as possible. This paper describes the differences between the Models 20 and 40, which have basically the same internal engine, and the Model 60, which has additional hardware to give it improved performance. The paper begins with a description of what cache and TLBs (translation look-aside buffers) are, and explains how they affect the performance of a processor.
{"title":"Hardware differences in the 9373 and 9375 processors","authors":"L. Curley, J. Kuruts, J. Myers","doi":"10.1145/62185.62188","DOIUrl":"https://doi.org/10.1145/62185.62188","url":null,"abstract":"In order to have a broad range of performance in processors, more than one model must exist. A family of processors infers systems with enough commonality that a smaller model can be upgraded to a larger one with minimum effort by retaining as much of the existing hardware as possible. This paper describes the differences between the Models 20 and 40, which have basically the same internal engine, and the Model 60, which has additional hardware to give it improved performance. The paper begins with a description of what cache and TLBs (translation look-aside buffers) are, and explains how they affect the performance of a processor.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128653529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The internal 370 mode (I370) is a high level microprogramming interface. It significantly improves microcode development productivity and portability.I370 is a subset of the S/370 architecture and has special functions for access to non-S/370 system resources. It facilitates the utilization of existing high-level languages for microprogramming.In general, I370 can be supported by any S/370 CPU, independent of its internal design and implementation. It is used in the IBM 9377 Model 90 system to implement major parts of S/370 microcode.
内部370模式(I370)是一个高级微编程接口。它显著提高了微码开发的生产力和可移植性。I370是S/370架构的一个子集，具有访问非S/370系统资源的特殊功能。它有利于利用现有的高级语言进行微程序设计。总的来说，I370可以被任何S/370 CPU支持，而不受其内部设计和实现的影响。它在IBM 9377 Model 90系统中用于实现S/370微码的主要部分。
{"title":"I370 - a new dimension of microprogramming","authors":"J. Maergner, Hartmut R. Schwermer","doi":"10.1145/62185.62189","DOIUrl":"https://doi.org/10.1145/62185.62189","url":null,"abstract":"The internal 370 mode (I370) is a high level microprogramming interface. It significantly improves microcode development productivity and portability.I370 is a subset of the S/370 architecture and has special functions for access to non-S/370 system resources. It facilitates the utilization of existing high-level languages for microprogramming.In general, I370 can be supported by any S/370 CPU, independent of its internal design and implementation. It is used in the IBM 9377 Model 90 system to implement major parts of S/370 microcode.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130095509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The IBM 9370 processor family uses System/370 (S/370) architecture, which consists of three parts: the central processing unit (CPU), memory, and I/O control. This paper explains how the 9373 and 9375 CPU instruction processing cards fetch and execute S/370 instructions.To obtain the maximum performance, the CPU is designed as a pipelined processor. Pipelining is a method used in processor design to optimize performance of a sequential stream of instructions. In a sequential stream of instructions, the processor knows what the next instruction is before the current one is completed; consequently, it can begin execution of it. In some cases, the processor can start some phase of the execution of several instructions before executing the current one, thus giving depth to the pipe. The 9373 and 9375 CPU cards take full advantage of pipelining to deliver optimum performance.
IBM 9370处理器系列采用System/370 (S/370)架构，由三部分组成:中央处理器(CPU)、内存和I/O控制。本文阐述了9373和9375 CPU指令处理卡如何获取和执行S/370指令。为了获得最大的性能，CPU被设计成流水线处理器。流水线是处理器设计中用于优化顺序指令流性能的一种方法。在顺序指令流中，处理器在当前指令完成之前知道下一条指令是什么;因此，它可以开始执行它。在某些情况下，处理器可以在执行当前指令之前开始执行几个指令的某个阶段，从而赋予管道深度。9373和9375 CPU卡充分利用流水线来提供最佳性能。
{"title":"The 9373 and 9375 pipelined processing unit","authors":"R. Kalla","doi":"10.1145/62185.62187","DOIUrl":"https://doi.org/10.1145/62185.62187","url":null,"abstract":"The IBM 9370 processor family uses System/370 (S/370) architecture, which consists of three parts: the central processing unit (CPU), memory, and I/O control. This paper explains how the 9373 and 9375 CPU instruction processing cards fetch and execute S/370 instructions.To obtain the maximum performance, the CPU is designed as a pipelined processor. Pipelining is a method used in processor design to optimize performance of a sequential stream of instructions. In a sequential stream of instructions, the processor knows what the next instruction is before the current one is completed; consequently, it can begin execution of it. In some cases, the processor can start some phase of the execution of several instructions before executing the current one, thus giving depth to the pipe. The 9373 and 9375 CPU cards take full advantage of pipelining to deliver optimum performance.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134177394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper develops a high level view of the central electronics complex in the 9373 and 9375 systems, showing how the hardware and microcode elements combine to create a central processor as defined by the System/370 architecture. Within the context of this discussion, the logical subsystems described here will be defined as the working base architecture. The hardware implementation of the central processor will be examined in detail, both in terms of hardware subsystems, and as resources to be used by the various microprograms to provide the correct System/370 interface and function.
{"title":"Implementing a mainframe architecture in a 9370 processor","authors":"James Mitchell","doi":"10.1145/62185.62186","DOIUrl":"https://doi.org/10.1145/62185.62186","url":null,"abstract":"This paper develops a high level view of the central electronics complex in the 9373 and 9375 systems, showing how the hardware and microcode elements combine to create a central processor as defined by the System/370 architecture. Within the context of this discussion, the logical subsystems described here will be defined as the working base architecture. The hardware implementation of the central processor will be examined in detail, both in terms of hardware subsystems, and as resources to be used by the various microprograms to provide the correct System/370 interface and function.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133147622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes how "correct" microcode can be produced through the use of mathematical logic and formal design methods. The use of these techniques to derive correct microcode for the IMS T800 floating point transputer from a mathematical specification is discussed. This experience on the IMS T800 has shown that this approach provides the opportunity to produce designs with a higher certainty of correctness in significantly less time as compared with "traditional" design techniques. These techniques are currently being applied to the construction of correct specifications at the hardware description language level. This work is attempting to incorporate mathematical logic and formal design methods into the INMOS CAD system so that their use becomes the standard way of producing correct VLSI devices.
{"title":"Using mathematical logic and formal methods to write correct microcode","authors":"D. Shepherd","doi":"10.1145/62197.62211","DOIUrl":"https://doi.org/10.1145/62197.62211","url":null,"abstract":"This paper describes how \"correct\" microcode can be produced through the use of mathematical logic and formal design methods. The use of these techniques to derive correct microcode for the IMS T800 floating point transputer from a mathematical specification is discussed. This experience on the IMS T800 has shown that this approach provides the opportunity to produce designs with a higher certainty of correctness in significantly less time as compared with \"traditional\" design techniques. These techniques are currently being applied to the construction of correct specifications at the hardware description language level. This work is attempting to incorporate mathematical logic and formal design methods into the INMOS CAD system so that their use becomes the standard way of producing correct VLSI devices.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132696164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
At the risk of flaunting a marginal grasp of the obvious I would like to make a few observations on the division of fixed point numbers.
冒着炫耀自己对显而易见的东西把握不够的风险，我想对定点数的除法做一些观察。
{"title":"A Note on Division of Positive Integers","authors":"F. Wilson","doi":"10.1145/62197.1096672","DOIUrl":"https://doi.org/10.1145/62197.1096672","url":null,"abstract":"At the risk of flaunting a marginal grasp of the obvious I would like to make a few observations on the division of fixed point numbers.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114563748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HILEVEL's DS3700 Series Emulyzers provides full microcode development support. The DS3700 combined with HALE (an advanced retargetable Macro-Meta Assembler), with software for firmware integration and debug, and with a host computer provides a complete microcode development system.
{"title":"HILEVEL microcode development system","authors":"K. Edwards","doi":"10.1145/16360.1096735","DOIUrl":"https://doi.org/10.1145/16360.1096735","url":null,"abstract":"HILEVEL's DS3700 Series Emulyzers provides full microcode development support. The DS3700 combined with HALE (an advanced retargetable Macro-Meta Assembler), with software for firmware integration and debug, and with a host computer provides a complete microcode development system.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125282402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This note describes a suite of microarchitectures that has been developed for evaluating microcode compilers. These architectures are not especially appropriate for the interpretation of "normal" instruction set architectures owing primarily to the lack of efficient facilities for buffering and decoding ISA level instructions. Also, a single-level, nonpartitioned control store organization is used that may not be the optimal choice for the architectures in this family.
{"title":"A suite of microarchitectures for evaluating microcode compilers for other than for ISA interpretation","authors":"J. Linn","doi":"10.1145/16360.1096743","DOIUrl":"https://doi.org/10.1145/16360.1096743","url":null,"abstract":"This note describes a suite of microarchitectures that has been developed for evaluating microcode compilers. These architectures are not especially appropriate for the interpretation of \"normal\" instruction set architectures owing primarily to the lack of efficient facilities for buffering and decoding ISA level instructions. Also, a single-level, nonpartitioned control store organization is used that may not be the optimal choice for the architectures in this family.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129127949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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