Pub Date : 2022-11-18DOI: 10.1142/s0218126623501645
Adnan Ramakic, Z. Bundalo, D. Bundalo
{"title":"An Example of Solution for Data Preparation Required for Some Purposes of People Identification or Re-Identification","authors":"Adnan Ramakic, Z. Bundalo, D. Bundalo","doi":"10.1142/s0218126623501645","DOIUrl":"https://doi.org/10.1142/s0218126623501645","url":null,"abstract":"","PeriodicalId":14696,"journal":{"name":"J. Circuits Syst. Comput.","volume":"97 1","pages":"2350164:1-2350164:14"},"PeriodicalIF":0.0,"publicationDate":"2022-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89547692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-14DOI: 10.1142/s0218126623501621
Kavita K. Patil, T. Kumaran
{"title":"Congestion Detection and Alleviation Mechanism Using a Multi-Level Cluster Based Cuckoo Hosted Rider Search Multi-Hop Hierarchical Routing Protocol in Wireless Sensor Networks","authors":"Kavita K. Patil, T. Kumaran","doi":"10.1142/s0218126623501621","DOIUrl":"https://doi.org/10.1142/s0218126623501621","url":null,"abstract":"","PeriodicalId":14696,"journal":{"name":"J. Circuits Syst. Comput.","volume":"73 1","pages":"2350162:1-2350162:27"},"PeriodicalIF":0.0,"publicationDate":"2022-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90410737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-14DOI: 10.1142/s0218126623501086
S. Sanka, M. Sujatha, J. R. Rahul
Multilevel inverters have emerged as a viable alternative for various power electronic applications. It offers significant features in terms of reduced total harmonic distortion (THD) due to more number of output voltage levels, lower filter size, and voltage stress and reduced switching losses when compared to conventional two-level inverters. The classical topologies such as neutral point clamped, flying capacitor and cascaded H-bridge (CHB) are very popular for industrial applications. All these topologies have limitations in terms of more component count, capacitor voltage balancing for increased number of voltage levels. In this regard, multi-level DC link (MLDCL) inverter has been introduced as an improvement with respect to CHB MLI in terms of reduced switch count and is considered here for the study. This paper presents a single-phase MLDC link inverter with a modified carrier-based level-shifted phase disposition sinusoidal pulse width modulation (LS-PD-SPWM) technique. The proposed novel carrier PWM is compared with the conventional modulation techniques in terms of THD. The performance of the proposed modulation technique is analyzed through simulation studies in MATLAB software. A laboratory prototype model is developed in order to validate the experimental results.
{"title":"Improved Seven-Level Multilevel DC-Link Inverter with Novel Carrier PWM Technique","authors":"S. Sanka, M. Sujatha, J. R. Rahul","doi":"10.1142/s0218126623501086","DOIUrl":"https://doi.org/10.1142/s0218126623501086","url":null,"abstract":"Multilevel inverters have emerged as a viable alternative for various power electronic applications. It offers significant features in terms of reduced total harmonic distortion (THD) due to more number of output voltage levels, lower filter size, and voltage stress and reduced switching losses when compared to conventional two-level inverters. The classical topologies such as neutral point clamped, flying capacitor and cascaded H-bridge (CHB) are very popular for industrial applications. All these topologies have limitations in terms of more component count, capacitor voltage balancing for increased number of voltage levels. In this regard, multi-level DC link (MLDCL) inverter has been introduced as an improvement with respect to CHB MLI in terms of reduced switch count and is considered here for the study. This paper presents a single-phase MLDC link inverter with a modified carrier-based level-shifted phase disposition sinusoidal pulse width modulation (LS-PD-SPWM) technique. The proposed novel carrier PWM is compared with the conventional modulation techniques in terms of THD. The performance of the proposed modulation technique is analyzed through simulation studies in MATLAB software. A laboratory prototype model is developed in order to validate the experimental results.","PeriodicalId":14696,"journal":{"name":"J. Circuits Syst. Comput.","volume":"72 1","pages":"2350108:1-2350108:22"},"PeriodicalIF":0.0,"publicationDate":"2022-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86268537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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