Delay, power, skew, area, and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power, and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast, and accurate; for example, our algorithm can solve a 6201-wire-segment clock-free problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.
{"title":"Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation","authors":"C. C. Chen, Yao-Wen Chang, D. F. Wong","doi":"10.1109/DAC.1996.545610","DOIUrl":"https://doi.org/10.1109/DAC.1996.545610","url":null,"abstract":"Delay, power, skew, area, and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power, and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast, and accurate; for example, our algorithm can solve a 6201-wire-segment clock-free problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115562911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The arithmetic functions, as a subclass of Boolean functions, have very compact descriptions in the AND and XOR operators. Any n-bit adder is a prime example. This paper presents a multilevel logic synthesis method which is particularly suited for arithmetic functions and utilizes their natural representations in the field GF(2). Algebraic factorization is performed to reduce the literal count. A direct translation of the AND/XOR representations of arithmetic functions into multilevel networks often results in excessive area, mainly due to the large area cost of XOR gates. We present a process of redundancy removal which reduces many XOR gates to single AND or OR gates without altering the functional behavior of the network. The redundancy removal process requires only to simulate a small and decidable set of primary input patterns. Preliminary results show that our method produces circuits, before and after technology mapping, with area improvement averaging 17% when compared to Berkeley SIS 1.2. The run time is reduced by at least 50%. The resulting circuits also have good testability and power consumption properties.
{"title":"Multilevel logic synthesis for arithmetic functions","authors":"Chien-Chung Tsai, M. Marek-Sadowska","doi":"10.1109/DAC.1996.545580","DOIUrl":"https://doi.org/10.1109/DAC.1996.545580","url":null,"abstract":"The arithmetic functions, as a subclass of Boolean functions, have very compact descriptions in the AND and XOR operators. Any n-bit adder is a prime example. This paper presents a multilevel logic synthesis method which is particularly suited for arithmetic functions and utilizes their natural representations in the field GF(2). Algebraic factorization is performed to reduce the literal count. A direct translation of the AND/XOR representations of arithmetic functions into multilevel networks often results in excessive area, mainly due to the large area cost of XOR gates. We present a process of redundancy removal which reduces many XOR gates to single AND or OR gates without altering the functional behavior of the network. The redundancy removal process requires only to simulate a small and decidable set of primary input patterns. Preliminary results show that our method produces circuits, before and after technology mapping, with area improvement averaging 17% when compared to Berkeley SIS 1.2. The run time is reduced by at least 50%. The resulting circuits also have good testability and power consumption properties.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fabrizio Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto
This paper presents a novel optimization algorithm for FSM networks that relies on sequential test generation and redundancy removal. The implementation of the proposed approach, which is based on the exploitation of input don't care sequences through regular language intersection, is fully symbolic. Experimental results, obtained on a large set of standard benchmarks, improve over the ones of state-of-the-art methods.
{"title":"Symbolic optimization of FSM networks based on sequential ATPG techniques","authors":"Fabrizio Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto","doi":"10.1109/DAC.1996.545621","DOIUrl":"https://doi.org/10.1109/DAC.1996.545621","url":null,"abstract":"This paper presents a novel optimization algorithm for FSM networks that relies on sequential test generation and redundancy removal. The implementation of the proposed approach, which is based on the exploitation of input don't care sequences through regular language intersection, is fully symbolic. Experimental results, obtained on a large set of standard benchmarks, improve over the ones of state-of-the-art methods.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121293901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic, S. Srbljic
This paper provides a case study that shows how a demanding application stresses the capabilities of today's CAD tools, especially in the integration of products from multiple vendors. We relate our experiences in the design of a large, high-speed multiprocessor computer using state of the art CAD tools. All logic circuitry is targeted field-programmable devices (FPDs). This choice amplifies the difficulties associated with achieving a highspeed design, and places extra requirements on the CAD tools. Two main CAD systems are discussed in the paper: Cadence Logic Workbench (LWB) is employed for board-level design, and Altera MAX+plusII is used for implementation of logic circuits in FPDs. Each of these products is of great value for our project, bur the integration of the two is less than satisfactory. The paper describes a custom procedure that we developed for integrating sub-designs realized in FPDs (via MAX+plusII) into our board-level designs in LWB. We also discuss experiences with Logic Modelling Smart Models, for simulation of FPDs and other types of chips.
{"title":"Experience in designing a large-scale multiprocessor using field-programmable devices and advanced CAD tools","authors":"S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic, S. Srbljic","doi":"10.1109/DAC.1996.545614","DOIUrl":"https://doi.org/10.1109/DAC.1996.545614","url":null,"abstract":"This paper provides a case study that shows how a demanding application stresses the capabilities of today's CAD tools, especially in the integration of products from multiple vendors. We relate our experiences in the design of a large, high-speed multiprocessor computer using state of the art CAD tools. All logic circuitry is targeted field-programmable devices (FPDs). This choice amplifies the difficulties associated with achieving a highspeed design, and places extra requirements on the CAD tools. Two main CAD systems are discussed in the paper: Cadence Logic Workbench (LWB) is employed for board-level design, and Altera MAX+plusII is used for implementation of logic circuits in FPDs. Each of these products is of great value for our project, bur the integration of the two is less than satisfactory. The paper describes a custom procedure that we developed for integrating sub-designs realized in FPDs (via MAX+plusII) into our board-level designs in LWB. We also discuss experiences with Logic Modelling Smart Models, for simulation of FPDs and other types of chips.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126408854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
System-level presynthesis refers to the optimization of an input HDL description that produces an optimized HDL description suitable for subsequent synthesis tasks. In this paper, we present optimization of control flow in behavioral HDL descriptions using external Don't Care conditions. The optimizations are carried out using a tabular model of system functionality, called Timed Decision Tables or TDTs. TDT based optimization presented here have been implemented in a program called PUMPKIN. Optimization results from several examples show a reduction of 3-88% in the size of synthesized hardware circuits depending upon the external Don't Care information supplied by the user.
{"title":"HDL optimization using timed decision tables","authors":"Jian Li, Rajesh K. Gupta","doi":"10.1109/DAC.1996.545544","DOIUrl":"https://doi.org/10.1109/DAC.1996.545544","url":null,"abstract":"System-level presynthesis refers to the optimization of an input HDL description that produces an optimized HDL description suitable for subsequent synthesis tasks. In this paper, we present optimization of control flow in behavioral HDL descriptions using external Don't Care conditions. The optimizations are carried out using a tabular model of system functionality, called Timed Decision Tables or TDTs. TDT based optimization presented here have been implemented in a program called PUMPKIN. Optimization results from several examples show a reduction of 3-88% in the size of synthesized hardware circuits depending upon the external Don't Care information supplied by the user.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125615583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an environment and tool suite for automatic synthesis and optimization of low power circuits. POSE provides a unified framework for specifying and maintaining power relevant circuit information and means of estimating power consumption of a circuit using different load models. POSE also gives a set of options for making area-power trade-offs during logic optimization.
{"title":"POSE: power optimization and synthesis environment","authors":"S. Iman, Massoud Pedram","doi":"10.1145/240518.240522","DOIUrl":"https://doi.org/10.1145/240518.240522","url":null,"abstract":"Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an environment and tool suite for automatic synthesis and optimization of low power circuits. POSE provides a unified framework for specifying and maintaining power relevant circuit information and means of estimating power consumption of a circuit using different load models. POSE also gives a set of options for making area-power trade-offs during logic optimization.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125696853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional project design flow. The methodology has been used successfully to verify the protocols within a distributed shared memory machine. We consider the following to be the four main benefits to using the model checker. First, it ensures that there exists an accurate high-level machine readable system specification. Second, it allows high-level system verification early in the design phase. Third, it facilitates equivalence and refinement checking between the high-level specification, and the RTL implementation. Finally, and most importantly it uncovered many protocol specification and RTL implementation problems.
{"title":"Integrating formal verification methods with a conventional project design flow","authors":"Á. Eiríksson","doi":"10.1109/DAC.1996.545658","DOIUrl":"https://doi.org/10.1109/DAC.1996.545658","url":null,"abstract":"We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional project design flow. The methodology has been used successfully to verify the protocols within a distributed shared memory machine. We consider the following to be the four main benefits to using the model checker. First, it ensures that there exists an accurate high-level machine readable system specification. Second, it allows high-level system verification early in the design phase. Third, it facilitates equivalence and refinement checking between the high-level specification, and the RTL implementation. Finally, and most importantly it uncovered many protocol specification and RTL implementation problems.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"91 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132364787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The performance estimation of a target system at a higher level of abstraction is very important in hardware/software codesign. We focus on software performance estimation, including both the execution time and the code size. We present two estimation methods at different levels of abstraction for use in the POLIS hardware/software codesign system. The experimental results show that the accuracy of our methods is usually within /spl plusmn/20%.
{"title":"Efficient software performance estimation methods for hardware/software codesign","authors":"Kei Suzuki, A. Sangiovanni-Vincentelli","doi":"10.1145/240518.240633","DOIUrl":"https://doi.org/10.1145/240518.240633","url":null,"abstract":"The performance estimation of a target system at a higher level of abstraction is very important in hardware/software codesign. We focus on software performance estimation, including both the execution time and the code size. We present two estimation methods at different levels of abstraction for use in the POLIS hardware/software codesign system. The experimental results show that the accuracy of our methods is usually within /spl plusmn/20%.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133209352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC design process. In this tutorial, we look at the last decade's worth of progress on analog circuit synthesis and layout tools. We focus on the frontend and backend of analog and mixed-signal IC design flows. The tutorial summarizes the problems for which viable solutions are emerging, and those which are still unsolved.
{"title":"Synthesis tools for Mixed-Signal ICs: progress on frontend and backend strategies","authors":"L. Carley, G. Gielen, Rob A. Rutenbar, W. Sansen","doi":"10.1145/240518.240573","DOIUrl":"https://doi.org/10.1145/240518.240573","url":null,"abstract":"Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC design process. In this tutorial, we look at the last decade's worth of progress on analog circuit synthesis and layout tools. We focus on the frontend and backend of analog and mixed-signal IC design flows. The tutorial summarizes the problems for which viable solutions are emerging, and those which are still unsolved.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131886043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A divide and conquer algorithm for computing the parametric yield of large analog circuits is presented. The algorithm targets applications whose performance spreads could be highly nonlinear functions of a large number of stochastic process disturbances, and therefore can not easily be modeled by traditional response surface methods. The work addresses difficulties with modeling by adaptively constructing the model piece by piece, namely, by efficiently and recursively partitioning the disturbance space into several regions, each of which is then modeled by a local linear model. Local linear models are used because they are less sensitive to dimension than polynomial models. Moreover, the resulting model can be made to be more accurate in some regions compared to others. The number of simulations required in statistical modeling can therefore be reduced since only critical regions, which define the boundary of the feasible region in the space of process disturbances, are modeled highly accurately. The resulting models are then used as cheap surrogates for circuit simulation in Monte Carlo estimation of the parametric yield. Examples indicate the efficiency and accuracy of this approach.
{"title":"Computing parametric yield adaptively using local linear models","authors":"Mien Li, L. Milor","doi":"10.1109/DAC.1996.545686","DOIUrl":"https://doi.org/10.1109/DAC.1996.545686","url":null,"abstract":"A divide and conquer algorithm for computing the parametric yield of large analog circuits is presented. The algorithm targets applications whose performance spreads could be highly nonlinear functions of a large number of stochastic process disturbances, and therefore can not easily be modeled by traditional response surface methods. The work addresses difficulties with modeling by adaptively constructing the model piece by piece, namely, by efficiently and recursively partitioning the disturbance space into several regions, each of which is then modeled by a local linear model. Local linear models are used because they are less sensitive to dimension than polynomial models. Moreover, the resulting model can be made to be more accurate in some regions compared to others. The number of simulations required in statistical modeling can therefore be reduced since only critical regions, which define the boundary of the feasible region in the space of process disturbances, are modeled highly accurately. The resulting models are then used as cheap surrogates for circuit simulation in Monte Carlo estimation of the parametric yield. Examples indicate the efficiency and accuracy of this approach.","PeriodicalId":152966,"journal":{"name":"33rd Design Automation Conference Proceedings, 1996","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127054753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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