According to literature, designers spend up to 30% of the design time on optimizing data representations in signal processing architectures [13]. Reference implementations, mostly in high-level software languages, choose floating point representation for mathematical calculations, which are too resource-intensive for FPGA implementations in many cases. The task of conversion to bit-width-optimized fixed point representations is tedious and therefore warrants automation. Usually some analytical or simulation-based approach is used for this, but past works usually overcomplicate their mode of operation and are therefore not commonplace in FPGA design. In this work, it is shown that a simulation-based approach can be both fast, given modern hardware, as well as simple enough to be integrated into a modern design flow. Using a real-world design from a complex power quality measurement algorithm, this is demonstrated and evaluated. Our implementation was able to reach much better results by reducing the resource utilization by approximately 80%, compared to the bit-widths proposed by a field expert while retaining the accuracy needed for the target application.
{"title":"Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration","authors":"Johannes Knödtel, M. Reichenbach","doi":"10.1145/3579170.3579257","DOIUrl":"https://doi.org/10.1145/3579170.3579257","url":null,"abstract":"According to literature, designers spend up to 30% of the design time on optimizing data representations in signal processing architectures [13]. Reference implementations, mostly in high-level software languages, choose floating point representation for mathematical calculations, which are too resource-intensive for FPGA implementations in many cases. The task of conversion to bit-width-optimized fixed point representations is tedious and therefore warrants automation. Usually some analytical or simulation-based approach is used for this, but past works usually overcomplicate their mode of operation and are therefore not commonplace in FPGA design. In this work, it is shown that a simulation-based approach can be both fast, given modern hardware, as well as simple enough to be integrated into a modern design flow. Using a real-world design from a complex power quality measurement algorithm, this is demonstrated and evaluated. Our implementation was able to reach much better results by reducing the resource utilization by approximately 80%, compared to the bit-widths proposed by a field expert while retaining the accuracy needed for the target application.","PeriodicalId":153341,"journal":{"name":"Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114460923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems","authors":"","doi":"10.1145/3579170","DOIUrl":"https://doi.org/10.1145/3579170","url":null,"abstract":"","PeriodicalId":153341,"journal":{"name":"Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133811930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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