The popularity of software radios is increasing, as they have become one of the important emerging technologies in mobile communications. One of the major challenges during development of mobile communications hardware is the inevitable low power requirement. In this paper, we investigate power management for software radios. The use of resolution adaptive analog to digital converters as well as the flexibility of the modulation schemes that a re-configurable radio provides is investigated. The concept of a resolution adaptive analog to digital converter is to trade performance for energy efficiency. The energy delay product is used to evaluate the performance versus energy tradeoffs and an adaptive power management method is proposed.
{"title":"Adaptive power management in software radios using resolution adaptive analog to digital converters","authors":"D. Hostetler, Yuan Xie","doi":"10.1109/ISVLSI.2005.14","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.14","url":null,"abstract":"The popularity of software radios is increasing, as they have become one of the important emerging technologies in mobile communications. One of the major challenges during development of mobile communications hardware is the inevitable low power requirement. In this paper, we investigate power management for software radios. The use of resolution adaptive analog to digital converters as well as the flexibility of the modulation schemes that a re-configurable radio provides is investigated. The concept of a resolution adaptive analog to digital converter is to trade performance for energy efficiency. The energy delay product is used to evaluate the performance versus energy tradeoffs and an adaptive power management method is proposed.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128048212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we investigate the problem of power optimization in CMOS circuits using gate sizing and voltage selection for a given clock period specification. Several solutions have been proposed for power optimization during gate sizing and voltage selection. Since the problem formulation is nonlinear in nature, nonlinear programming (NLP) based solutions yield better accuracy, however, convergence is difficult for large circuits. On the other hand, heuristic solutions result in faster but less accurate solutions. In this work, we propose a new algorithm for gate sizing and voltage selection based on NLP for power optimization. The algorithm uses gate level heuristics for delay assignment which disassociates the delays of all the paths to the individual gate level, and each gate is then separately optimized for power with its delay constraint. Since the optimization is done at the individual gate level, NLP converges quickly while maintaining accuracy. Experimental results are presented for ISCAS benchmarks which clearly illustrate the efficacy of the proposed solution.
{"title":"A nonlinear programming based power optimization methodology for gate sizing and voltage selection","authors":"V. Mahalingam, N. Ranganathan","doi":"10.1109/ISVLSI.2005.12","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.12","url":null,"abstract":"In this paper, we investigate the problem of power optimization in CMOS circuits using gate sizing and voltage selection for a given clock period specification. Several solutions have been proposed for power optimization during gate sizing and voltage selection. Since the problem formulation is nonlinear in nature, nonlinear programming (NLP) based solutions yield better accuracy, however, convergence is difficult for large circuits. On the other hand, heuristic solutions result in faster but less accurate solutions. In this work, we propose a new algorithm for gate sizing and voltage selection based on NLP for power optimization. The algorithm uses gate level heuristics for delay assignment which disassociates the delays of all the paths to the individual gate level, and each gate is then separately optimized for power with its delay constraint. Since the optimization is done at the individual gate level, NLP converges quickly while maintaining accuracy. Experimental results are presented for ISCAS benchmarks which clearly illustrate the efficacy of the proposed solution.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123204836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a turbo soft-in soft-out (SISO) decoder based on max-log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique based on branch metric normalization is introduced to improve the speed performance of the decoder. The turbo decoder with the proposed technique has been synthesized to evaluate its power consumption and area usage using a 0.18um standard CMOS cell library. It is shown that while power consumption and area usage change slightly with our technique, it achieves up to 58% speed-up compared to a conventional SISO decoder architecture.
{"title":"High speed max-log-MAP turbo SISO decoder implementation using branch metric normalization","authors":"J. H. Han, A. Erdogan, T. Arslan","doi":"10.1109/ISVLSI.2005.37","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.37","url":null,"abstract":"The authors present a turbo soft-in soft-out (SISO) decoder based on max-log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique based on branch metric normalization is introduced to improve the speed performance of the decoder. The turbo decoder with the proposed technique has been synthesized to evaluate its power consumption and area usage using a 0.18um standard CMOS cell library. It is shown that while power consumption and area usage change slightly with our technique, it achieves up to 58% speed-up compared to a conventional SISO decoder architecture.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122947559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A redundant bit adder (RBA) and a divider, both implemented in output prediction logic (OPL), are presented. By combining the carry-free nature of the redundant number system and the high-speed characteristics of OPL, the performance of the arithmetic blocks was tremendously improved. Fabricated in 0.18/spl mu/m/1.8V CMOS, the adder achieves a measured delay of 211ps (2.4 fanout-of-four inverter delays), which is significantly faster than any previously published RBAs. The divider implemented in the same technology can achieve an operating frequency of 1.25GHz.
{"title":"High speed redundant adder and divider in output prediction logic","authors":"Xinyu Guo, C. Sechen","doi":"10.1109/ISVLSI.2005.38","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.38","url":null,"abstract":"A redundant bit adder (RBA) and a divider, both implemented in output prediction logic (OPL), are presented. By combining the carry-free nature of the redundant number system and the high-speed characteristics of OPL, the performance of the arithmetic blocks was tremendously improved. Fabricated in 0.18/spl mu/m/1.8V CMOS, the adder achieves a measured delay of 211ps (2.4 fanout-of-four inverter delays), which is significantly faster than any previously published RBAs. The divider implemented in the same technology can achieve an operating frequency of 1.25GHz.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122065800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Quantum computing is one of the most promising emerging technologies of the future. Reversible circuits are an important class of quantum circuits. In this paper, we investigate the problem of optimally synthesizing four-qubit reversible circuits. We present an enhanced bidirectional synthesis approach. Due to the super-exponential increase on the memory requirement, all the existing methods can only perform four steps for the CNP (Control-Not gate, NOT gate, and Peres gate) library. Our novel method can achieve 12 steps. As a result, we augment the number of circuits that can be optimally synthesized by over 5/sup */10/sup 6/ times. Moreover, our approach is faster than the existing approaches by orders of magnitude. The promising experimental results demonstrate the effectiveness of our approach.
{"title":"Bi-direction synthesis for reversible circuits","authors":"Guowu Yang, Xiaoyu Song, W. Hung, M. Perkowski","doi":"10.1109/ISVLSI.2005.21","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.21","url":null,"abstract":"Quantum computing is one of the most promising emerging technologies of the future. Reversible circuits are an important class of quantum circuits. In this paper, we investigate the problem of optimally synthesizing four-qubit reversible circuits. We present an enhanced bidirectional synthesis approach. Due to the super-exponential increase on the memory requirement, all the existing methods can only perform four steps for the CNP (Control-Not gate, NOT gate, and Peres gate) library. Our novel method can achieve 12 steps. As a result, we augment the number of circuits that can be optimally synthesized by over 5/sup */10/sup 6/ times. Moreover, our approach is faster than the existing approaches by orders of magnitude. The promising experimental results demonstrate the effectiveness of our approach.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122813886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junhao Shi, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel
Automatic test pattern generation (ATPG) based on Boolean satisfiability (SAT) has been proposed as an alternative to classical search algorithms. SAT-based ATPG turned out to be more robust and more effective by formulating the problem as a set of equations. In this paper, we present an efficient ATPG algorithm that makes use of powerful SAT-solving techniques. Problem specific heuristics are applied to guide the search. In contrast to previous SAT-based algorithms, the new approach can also cope with tri-states. The algorithm has been implemented as the tool PASSAT. Experimental results on large industrial circuits are given to demonstrate the quality and efficiency of the algorithm.
{"title":"PASSAT: efficient SAT-based test pattern generation for industrial circuits","authors":"Junhao Shi, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel","doi":"10.1109/ISVLSI.2005.55","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.55","url":null,"abstract":"Automatic test pattern generation (ATPG) based on Boolean satisfiability (SAT) has been proposed as an alternative to classical search algorithms. SAT-based ATPG turned out to be more robust and more effective by formulating the problem as a set of equations. In this paper, we present an efficient ATPG algorithm that makes use of powerful SAT-solving techniques. Problem specific heuristics are applied to guide the search. In contrast to previous SAT-based algorithms, the new approach can also cope with tri-states. The algorithm has been implemented as the tool PASSAT. Experimental results on large industrial circuits are given to demonstrate the quality and efficiency of the algorithm.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121861827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a code refactoring methodology for the high-level analog synthesis is presented. It restructures, refines, and simplifies an analog behavioral model written in VHDL-AMS. Through code refactoring one improves the comprehensibility, expandability and reusability of the behavioral model and brings the model to a necessary preliminary stage for the actual circuit synthesis. This approach supports the top-down hierarchical design flow for analog and mixed-signal application.
{"title":"RAMS: a VHDL-AMS code refactoring tool supporting high level analog synthesis","authors":"K. Zeng, S. Huss","doi":"10.1109/ISVLSI.2005.60","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.60","url":null,"abstract":"In this paper, a code refactoring methodology for the high-level analog synthesis is presented. It restructures, refines, and simplifies an analog behavioral model written in VHDL-AMS. Through code refactoring one improves the comprehensibility, expandability and reusability of the behavioral model and brings the model to a necessary preliminary stage for the actual circuit synthesis. This approach supports the top-down hierarchical design flow for analog and mixed-signal application.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128800365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8x8-bit hybrid wave-pipeline multiplier using carry-save adder technique is described. The multiplier has been designed using TSMC 180nm. The basic cells in multiplier are designed to have small propagation delay and delay variation. The hybrid wave-pipelined multiplier is able to achieve 2.86 billion multiplications per second.
{"title":"A high performance hybrid wave-pipelined multiplier","authors":"S. Tatapudi, J. Delgado-Frías","doi":"10.1109/ISVLSI.2005.7","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.7","url":null,"abstract":"The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8x8-bit hybrid wave-pipeline multiplier using carry-save adder technique is described. The multiplier has been designed using TSMC 180nm. The basic cells in multiplier are designed to have small propagation delay and delay variation. The hybrid wave-pipelined multiplier is able to achieve 2.86 billion multiplications per second.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133716952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10MHz. The proposed modulator architecture employs the 2nd order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A data-weighted-averaging technique eliminates tones generated by the multibit digital-to-analog converter (DAC) nonlinearity improving the spurious free dynamic range (SFDR) and intermodulation distortion performance. The modulator is designed in 0.18/spl mu/m CMOS process and operates at 1.8V supply voltage. It achieves 62.86 dB signal-to-noise plus distortion ratio (SNDR) in the 10MHz signal bandwidth, a SFDR of 82.2dB and IMD3 of -77.5dB.
{"title":"A modified cascaded sigma-delta modulator with improved linearity","authors":"A. Rusu, M. Ismail, H. Tenhunen","doi":"10.1109/ISVLSI.2005.10","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.10","url":null,"abstract":"This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10MHz. The proposed modulator architecture employs the 2nd order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A data-weighted-averaging technique eliminates tones generated by the multibit digital-to-analog converter (DAC) nonlinearity improving the spurious free dynamic range (SFDR) and intermodulation distortion performance. The modulator is designed in 0.18/spl mu/m CMOS process and operates at 1.8V supply voltage. It achieves 62.86 dB signal-to-noise plus distortion ratio (SNDR) in the 10MHz signal bandwidth, a SFDR of 82.2dB and IMD3 of -77.5dB.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"571 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131551908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Among many recently proposed on-chip jitter measurement designs, Vernier delay line (VDL) is one of the most widely adopted methods that can achieve fine resolution. However, there are two major design challenges: the first is the mismatching of delay buffers; the second is the unavailability of an on-chip jitter free reference signal. To overcome these two challenges, we propose a self-refereed on-chip jitter measurement circuit. This measurement circuit eliminates the requirement to a jitter free reference signal. In addition, it utilizes Vernier oscillators to alleviate the mismatching effect in Vernier lines. Using this design, the jitter distribution and jitter RMS value can be characterized. To validate the design, the circuit has been implemented using IBM 7 HP 0.18um CMOS technology.
在最近提出的许多片上抖动测量设计中，游标延迟线(VDL)是采用最广泛的一种可以实现精细分辨率的方法。然而，有两个主要的设计挑战:第一是延迟缓冲器的不匹配;第二是片上无抖动参考信号的不可用性。为了克服这两个挑战，我们提出了一种自参考片上抖动测量电路。这种测量电路消除了对无抖动参考信号的要求。此外，它利用游标振荡器来减轻游标线的不匹配效应。利用该设计，可以表征抖动分布和抖动均方根值。为了验证该设计，电路已使用IBM 7 HP 0.18um CMOS技术实现。
{"title":"Self-refereed on-chip jitter measurement circuit using Vernier oscillators","authors":"T. Xia, Hao Zheng, Jing Li, Ahmed Y. Ginawi","doi":"10.1109/ISVLSI.2005.66","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.66","url":null,"abstract":"Among many recently proposed on-chip jitter measurement designs, Vernier delay line (VDL) is one of the most widely adopted methods that can achieve fine resolution. However, there are two major design challenges: the first is the mismatching of delay buffers; the second is the unavailability of an on-chip jitter free reference signal. To overcome these two challenges, we propose a self-refereed on-chip jitter measurement circuit. This measurement circuit eliminates the requirement to a jitter free reference signal. In addition, it utilizes Vernier oscillators to alleviate the mismatching effect in Vernier lines. Using this design, the jitter distribution and jitter RMS value can be characterized. To validate the design, the circuit has been implemented using IBM 7 HP 0.18um CMOS technology.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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