Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185386
Thomas Popp
Implementation attacks pose a serious threat to the security of cryptographic algorithms and protocols. In such attacks, not the abstract descriptions of cryptographic methods are attacked but their practical realizations in cryptographic devices. This opens up a wide range of powerful attacks, which are introduced in this article. Also the main approaches to counteract implementation attacks are discussed.
{"title":"An introduction to implementation attacks and countermeasures","authors":"Thomas Popp","doi":"10.1109/MEMCOD.2009.5185386","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185386","url":null,"abstract":"Implementation attacks pose a serious threat to the security of cryptographic algorithms and protocols. In such attacks, not the abstract descriptions of cryptographic methods are attacked but their practical realizations in cryptographic devices. This opens up a wide range of powerful attacks, which are introduced in this article. Also the main approaches to counteract implementation attacks are discussed.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130292165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185378
O. Sarbishei, M. Tabandeh, B. Alizadeh, M. Fujita
Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency compared to the conventional optimization approaches.
{"title":"High-level optimization of integer multipliers over a finite bit-width with verification capabilities","authors":"O. Sarbishei, M. Tabandeh, B. Alizadeh, M. Fujita","doi":"10.1109/MEMCOD.2009.5185378","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185378","url":null,"abstract":"Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency compared to the conventional optimization approaches.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185387
M. Rinard
Survival is a key concern of many complex systems. A standard approach to maximizing the likelihood of survival is to attempt to produce a system that is as free of errors as possible. We instead propose a methodology that changes the semantics of the underlying development and execution environments to cleanly and simply obtain survival guarantees that are difficult if not impossible to obtain with standard techniques. Examples of survival properties include continued execution in the face of addressing errors and guaranteed bounds on the amount of memory required during any execution of the system (even in the face of dynamic memory allocation).We summarize results for software implementations of these techniques and discuss issues and advantages that arise in the context of hardware implementations.
{"title":"Survival strategies for synthesized hardware systems","authors":"M. Rinard","doi":"10.1109/MEMCOD.2009.5185387","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185387","url":null,"abstract":"Survival is a key concern of many complex systems. A standard approach to maximizing the likelihood of survival is to attempt to produce a system that is as free of errors as possible. We instead propose a methodology that changes the semantics of the underlying development and execution environments to cleanly and simply obtain survival guarantees that are difficult if not impossible to obtain with standard techniques. Examples of survival properties include continued execution in the face of addressing errors and guaranteed bounds on the amount of memory required during any execution of the system (even in the face of dynamic memory allocation).We summarize results for software implementations of these techniques and discuss issues and advantages that arise in the context of hardware implementations.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125080202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185388
M. Bozzano, A. Cimatti, Marco Roveri, J. Katoen, V. Y. Nguyen, T. Noll
This paper presents a model-based approach to system-software co-engineering which is focused on aerospace systems but is relevant to a much wider class of dependable systems. We present the main ingredients of the SLIM modeling language and give a precise interpretation of SLIM models by providing a formal semantics using networks of event-data automata. The major distinguishing aspects of this component-based approach are the possibility to describe nominal hardware and software operations, hybrid (and timing) aspects, as well as probabilistic faults and their propagation and recovery. As our approach bears strong resemblance to the standardized AADL (Architecture Analysis and Design Language), a secondary contribution of this paper is a formal semantics of a large fragment of AADL including its Error Model Annex.
{"title":"Codesign of dependable systems: A component-based modeling language","authors":"M. Bozzano, A. Cimatti, Marco Roveri, J. Katoen, V. Y. Nguyen, T. Noll","doi":"10.1109/MEMCOD.2009.5185388","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185388","url":null,"abstract":"This paper presents a model-based approach to system-software co-engineering which is focused on aerospace systems but is relevant to a much wider class of dependable systems. We present the main ingredients of the SLIM modeling language and give a precise interpretation of SLIM models by providing a formal semantics using networks of event-data automata. The major distinguishing aspects of this component-based approach are the possibility to describe nominal hardware and software operations, hybrid (and timing) aspects, as well as probabilistic faults and their propagation and recovery. As our approach bears strong resemblance to the standardized AADL (Architecture Analysis and Design Language), a secondary contribution of this paper is a formal semantics of a large fragment of AADL including its Error Model Annex.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123217003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-01DOI: 10.1109/MEMCOD.2009.5185389
Fabrizio Ferrandi, M. Lattuada, C. Pilato, Antonino Tumeo
The speed-up estimation of parallelized code is crucial to efficiently compare different parallelization techniques or task graph transformations. Unfortunately, most of the time, during the parallelization of a specification, the information that can be extracted by profiling the corresponding sequential code (e.g. the most executed paths) are not properly taken into account. In particular, correlating sequential path profiling with the corresponding parallelized code can help in the identification of code hot spots, opening new possibilities for automatic parallelization. For this reason, starting from a well-known profiling technique, the Efficient Path Profiling, we propose a methodology that estimates the speed-up of a parallelized specification, just using the corresponding hierarchical task graph representation and the information coming from the dynamic profiling of the initial sequential specification. Experimental results show that the proposed solution outperforms existing approaches.
{"title":"Performance estimation for task graphs combining sequential path profiling and control dependence regions","authors":"Fabrizio Ferrandi, M. Lattuada, C. Pilato, Antonino Tumeo","doi":"10.1109/MEMCOD.2009.5185389","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185389","url":null,"abstract":"The speed-up estimation of parallelized code is crucial to efficiently compare different parallelization techniques or task graph transformations. Unfortunately, most of the time, during the parallelization of a specification, the information that can be extracted by profiling the corresponding sequential code (e.g. the most executed paths) are not properly taken into account. In particular, correlating sequential path profiling with the corresponding parallelized code can help in the identification of code hot spots, opening new possibilities for automatic parallelization. For this reason, starting from a well-known profiling technique, the Efficient Path Profiling, we propose a methodology that estimates the speed-up of a parallelized specification, just using the corresponding hierarchical task graph representation and the information coming from the dynamic profiling of the initial sequential specification. Experimental results show that the proposed solution outperforms existing approaches.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128103933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：