Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185372
A. Pnueli, U. Klein
The paper investigates a development process for reactive programs, in which the program is automatically generated (synthesized) from a high-level temporal specification. The method is based on previous results that proposed a similar synthesis method for the automatic construction of hardware designs from their temporal specifications. Thus, the work reported here can be viewed as a generalization of existing methods for the synthesis of synchronous reactive systems into the synthesis of asynchronous systems. In the synchronous case it was possible to identify a restricted subclass of formulas and present an algorithm that solves the synthesis problem for these restricted specifications in polynomial time. Here the results are less definitive in the sense that we can offer some heuristics that may provide polynomial-time solutions only in some of the cases.
{"title":"Synthesis of programs from temporal property specifications","authors":"A. Pnueli, U. Klein","doi":"10.1109/MEMCOD.2009.5185372","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185372","url":null,"abstract":"The paper investigates a development process for reactive programs, in which the program is automatically generated (synthesized) from a high-level temporal specification. The method is based on previous results that proposed a similar synthesis method for the automatic construction of hardware designs from their temporal specifications. Thus, the work reported here can be viewed as a generalization of existing methods for the synthesis of synchronous reactive systems into the synthesis of asynchronous systems. In the synchronous case it was possible to identify a restricted subclass of formulas and present an algorithm that solves the synthesis problem for these restricted specifications in polynomial time. Here the results are less definitive in the sense that we can offer some heuristics that may provide polynomial-time solutions only in some of the cases.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117196155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185374
Jeong-Han Yun, Chul-Joo Kim, Sunae Seo, Taisook Han, K. Choe
Esterel is an imperative synchronous language for control-dominant reactive systems. The combination of imperative structures and the perfect synchrony hypothesis often result in schizophrenic statements. Previous studies explain the characteristics of schizophrenia as the instantaneous reentrance to block statements: local signal declarations and parallel statements. In practice, however, most instantly-reentered block statements do not cause any problems in Esterel compilation. In this paper, we refine schizophrenic problems in terms of signal emissions, and suggest an algorithm to detect harmful schizophrenia using reachability on control flow graphs (CFGs) in Esterel. Our algorithm performs well in analyzing practical programs. Moreover, it can be easily applied to existing compilers.
{"title":"Refining schizophrenia via graph reachability in Esterel","authors":"Jeong-Han Yun, Chul-Joo Kim, Sunae Seo, Taisook Han, K. Choe","doi":"10.1109/MEMCOD.2009.5185374","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185374","url":null,"abstract":"Esterel is an imperative synchronous language for control-dominant reactive systems. The combination of imperative structures and the perfect synchrony hypothesis often result in schizophrenic statements. Previous studies explain the characteristics of schizophrenia as the instantaneous reentrance to block statements: local signal declarations and parallel statements. In practice, however, most instantly-reentered block statements do not cause any problems in Esterel compilation. In this paper, we refine schizophrenic problems in terms of signal emissions, and suggest an algorithm to detect harmful schizophrenia using reachability on control flow graphs (CFGs) in Esterel. Our algorithm performs well in analyzing practical programs. Moreover, it can be easily applied to existing compilers.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129644175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185393
M. Vijayaraghavan, Arvind
We present a theory for modular refinement of Synchronous Sequential Circuits (SSMs) using Bounded Dataflow Networks (BDNs). We provide a procedure for implementing any SSM into an LI-BDN, a special class of BDNs with some good compositional properties. We show that the Latency-Insensitive property of LI-BDNs is preserved under parallel and iterative composition of LI-BDNs. Our theory permits one to make arbitrary cuts in an SSM and turn each of the parts into LI-BDNs without affecting the overall functionality. We can further refine each constituent LI-BDN into another LI-BDN which may take different number of cycles to compute. If the constituent LI-BDN is refined correctly we guarantee that the overall behavior would be cycle-accurate with respect to the original SSM. Thus one can replace, say a 3-ported register file in an SSM by a one-ported register file without affecting the correctness of the SSM. We give several examples to show how our theory supports a generalization of previous techniques for Latency-Insensitive refinements of SSMs.
{"title":"Bounded Dataflow Networks and Latency-Insensitive circuits","authors":"M. Vijayaraghavan, Arvind","doi":"10.1109/MEMCOD.2009.5185393","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185393","url":null,"abstract":"We present a theory for modular refinement of Synchronous Sequential Circuits (SSMs) using Bounded Dataflow Networks (BDNs). We provide a procedure for implementing any SSM into an LI-BDN, a special class of BDNs with some good compositional properties. We show that the Latency-Insensitive property of LI-BDNs is preserved under parallel and iterative composition of LI-BDNs. Our theory permits one to make arbitrary cuts in an SSM and turn each of the parts into LI-BDNs without affecting the overall functionality. We can further refine each constituent LI-BDN into another LI-BDN which may take different number of cycles to compute. If the constituent LI-BDN is refined correctly we guarantee that the overall behavior would be cycle-accurate with respect to the original SSM. Thus one can replace, say a 3-ported register file in an SSM by a one-ported register file without affecting the correctness of the SSM. We give several examples to show how our theory supports a generalization of previous techniques for Latency-Insensitive refinements of SSMs.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185373
Malay K. Ganai, Weihong Li
In practice, verification engines have to solve many checkers in a very tight time budget, especially, when the system to be analyzed is large, with many coverage criteria. To cope with such a situation, we propose improved and light-weight verification techniques that are built over the state-of-the-art engines such as bounded model checking (BMC), induction, and guided-simulation (directed testing). Specifically, we propose using control state reachability (CSR) information—obtained from a given software system—to strengthen our induction-based proof engine. We also propose identifying and using lighthouses (or guide-posts)—intermediate control states—to simplify and reduce BMC instances, and to guide a simulation engine. We schedule these engines suitably to maximize the resource utilization. We implemented our techniques in a tool ACE, and integrated it in an industry strength software verification platform F-Soft to provide a robust and precise analysis framework. We show effectiveness of ACE on several industry and public benchmarks in a comparative study.
{"title":"Bang for the buck: Improvising and scheduling verification engines for effective resource utilization","authors":"Malay K. Ganai, Weihong Li","doi":"10.1109/MEMCOD.2009.5185373","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185373","url":null,"abstract":"In practice, verification engines have to solve many checkers in a very tight time budget, especially, when the system to be analyzed is large, with many coverage criteria. To cope with such a situation, we propose improved and light-weight verification techniques that are built over the state-of-the-art engines such as bounded model checking (BMC), induction, and guided-simulation (directed testing). Specifically, we propose using control state reachability (CSR) information—obtained from a given software system—to strengthen our induction-based proof engine. We also propose identifying and using lighthouses (or guide-posts)—intermediate control states—to simplify and reduce BMC instances, and to guide a simulation engine. We schedule these engines suitably to maximize the resource utilization. We implemented our techniques in a tool ACE, and integrated it in an industry strength software verification platform F-Soft to provide a robust and precise analysis framework. We show effectiveness of ACE on several industry and public benchmarks in a comparative study.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127665098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185375
L. D. Guglielmo, F. Fummi, G. Pravadelli
The paper proposes a comprehensive methodology for property qualification based on a combination of dynamic and static techniques. In particular, given a set of properties defined to check the correctness of a design implementation, the methodology first evaluates property coverage, property overspecification, and it identifies vacuous properties. This is commonly performed by exploiting mutation analysis and automatic testbenches generation, i.e., dynamic strategies. This phase allows us to quickly evaluate the quality of properties with respect to the use of formal approaches. Then, a second phase, based on model checking, is applied to the restricted number of situations, where the dynamic approach is not exhaustive. Experimental results show the effectiveness and efficiency of the proposed methodology.
{"title":"The role of mutation analysis for property qualification","authors":"L. D. Guglielmo, F. Fummi, G. Pravadelli","doi":"10.1109/MEMCOD.2009.5185375","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185375","url":null,"abstract":"The paper proposes a comprehensive methodology for property qualification based on a combination of dynamic and static techniques. In particular, given a set of properties defined to check the correctness of a design implementation, the methodology first evaluates property coverage, property overspecification, and it identifies vacuous properties. This is commonly performed by exploiting mutation analysis and automatic testbenches generation, i.e., dynamic strategies. This phase allows us to quickly evaluate the quality of properties with respect to the use of formal approaches. Then, a second phase, based on model checking, is applied to the restricted number of situations, where the dynamic approach is not exhaustive. Experimental results show the effectiveness and efficiency of the proposed methodology.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130925212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185386
Thomas Popp
Implementation attacks pose a serious threat to the security of cryptographic algorithms and protocols. In such attacks, not the abstract descriptions of cryptographic methods are attacked but their practical realizations in cryptographic devices. This opens up a wide range of powerful attacks, which are introduced in this article. Also the main approaches to counteract implementation attacks are discussed.
{"title":"An introduction to implementation attacks and countermeasures","authors":"Thomas Popp","doi":"10.1109/MEMCOD.2009.5185386","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185386","url":null,"abstract":"Implementation attacks pose a serious threat to the security of cryptographic algorithms and protocols. In such attacks, not the abstract descriptions of cryptographic methods are attacked but their practical realizations in cryptographic devices. This opens up a wide range of powerful attacks, which are introduced in this article. Also the main approaches to counteract implementation attacks are discussed.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130292165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185378
O. Sarbishei, M. Tabandeh, B. Alizadeh, M. Fujita
Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency compared to the conventional optimization approaches.
{"title":"High-level optimization of integer multipliers over a finite bit-width with verification capabilities","authors":"O. Sarbishei, M. Tabandeh, B. Alizadeh, M. Fujita","doi":"10.1109/MEMCOD.2009.5185378","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185378","url":null,"abstract":"Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency compared to the conventional optimization approaches.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185387
M. Rinard
Survival is a key concern of many complex systems. A standard approach to maximizing the likelihood of survival is to attempt to produce a system that is as free of errors as possible. We instead propose a methodology that changes the semantics of the underlying development and execution environments to cleanly and simply obtain survival guarantees that are difficult if not impossible to obtain with standard techniques. Examples of survival properties include continued execution in the face of addressing errors and guaranteed bounds on the amount of memory required during any execution of the system (even in the face of dynamic memory allocation).We summarize results for software implementations of these techniques and discuss issues and advantages that arise in the context of hardware implementations.
{"title":"Survival strategies for synthesized hardware systems","authors":"M. Rinard","doi":"10.1109/MEMCOD.2009.5185387","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185387","url":null,"abstract":"Survival is a key concern of many complex systems. A standard approach to maximizing the likelihood of survival is to attempt to produce a system that is as free of errors as possible. We instead propose a methodology that changes the semantics of the underlying development and execution environments to cleanly and simply obtain survival guarantees that are difficult if not impossible to obtain with standard techniques. Examples of survival properties include continued execution in the face of addressing errors and guaranteed bounds on the amount of memory required during any execution of the system (even in the face of dynamic memory allocation).We summarize results for software implementations of these techniques and discuss issues and advantages that arise in the context of hardware implementations.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125080202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-13DOI: 10.1109/MEMCOD.2009.5185388
M. Bozzano, A. Cimatti, Marco Roveri, J. Katoen, V. Y. Nguyen, T. Noll
This paper presents a model-based approach to system-software co-engineering which is focused on aerospace systems but is relevant to a much wider class of dependable systems. We present the main ingredients of the SLIM modeling language and give a precise interpretation of SLIM models by providing a formal semantics using networks of event-data automata. The major distinguishing aspects of this component-based approach are the possibility to describe nominal hardware and software operations, hybrid (and timing) aspects, as well as probabilistic faults and their propagation and recovery. As our approach bears strong resemblance to the standardized AADL (Architecture Analysis and Design Language), a secondary contribution of this paper is a formal semantics of a large fragment of AADL including its Error Model Annex.
{"title":"Codesign of dependable systems: A component-based modeling language","authors":"M. Bozzano, A. Cimatti, Marco Roveri, J. Katoen, V. Y. Nguyen, T. Noll","doi":"10.1109/MEMCOD.2009.5185388","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185388","url":null,"abstract":"This paper presents a model-based approach to system-software co-engineering which is focused on aerospace systems but is relevant to a much wider class of dependable systems. We present the main ingredients of the SLIM modeling language and give a precise interpretation of SLIM models by providing a formal semantics using networks of event-data automata. The major distinguishing aspects of this component-based approach are the possibility to describe nominal hardware and software operations, hybrid (and timing) aspects, as well as probabilistic faults and their propagation and recovery. As our approach bears strong resemblance to the standardized AADL (Architecture Analysis and Design Language), a secondary contribution of this paper is a formal semantics of a large fragment of AADL including its Error Model Annex.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123217003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-01DOI: 10.1109/MEMCOD.2009.5185389
Fabrizio Ferrandi, M. Lattuada, C. Pilato, Antonino Tumeo
The speed-up estimation of parallelized code is crucial to efficiently compare different parallelization techniques or task graph transformations. Unfortunately, most of the time, during the parallelization of a specification, the information that can be extracted by profiling the corresponding sequential code (e.g. the most executed paths) are not properly taken into account. In particular, correlating sequential path profiling with the corresponding parallelized code can help in the identification of code hot spots, opening new possibilities for automatic parallelization. For this reason, starting from a well-known profiling technique, the Efficient Path Profiling, we propose a methodology that estimates the speed-up of a parallelized specification, just using the corresponding hierarchical task graph representation and the information coming from the dynamic profiling of the initial sequential specification. Experimental results show that the proposed solution outperforms existing approaches.
{"title":"Performance estimation for task graphs combining sequential path profiling and control dependence regions","authors":"Fabrizio Ferrandi, M. Lattuada, C. Pilato, Antonino Tumeo","doi":"10.1109/MEMCOD.2009.5185389","DOIUrl":"https://doi.org/10.1109/MEMCOD.2009.5185389","url":null,"abstract":"The speed-up estimation of parallelized code is crucial to efficiently compare different parallelization techniques or task graph transformations. Unfortunately, most of the time, during the parallelization of a specification, the information that can be extracted by profiling the corresponding sequential code (e.g. the most executed paths) are not properly taken into account. In particular, correlating sequential path profiling with the corresponding parallelized code can help in the identification of code hot spots, opening new possibilities for automatic parallelization. For this reason, starting from a well-known profiling technique, the Efficient Path Profiling, we propose a methodology that estimates the speed-up of a parallelized specification, just using the corresponding hierarchical task graph representation and the information coming from the dynamic profiling of the initial sequential specification. Experimental results show that the proposed solution outperforms existing approaches.","PeriodicalId":163970,"journal":{"name":"2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128103933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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