Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548429
U. Yaman, M. Dolen, A. Koku
This paper focuses on a novel command generator for servo-motor drives to be used as an integral part of their motion controllers. The method, which incorporates a new data compression algorithm, is capable of generating trajectory data at variable rates. In this paradigm, higher-order differences of a given trajectory (i.e. position) are first computed and thus the resulting data are compressed via the proposed technique. The generation of the commands is carried out according to the feedrate (i.e. the speed along the trajectory) set by the external logic dynamically. The paper discusses the implementation of the method on a Field Programmable Gate Array (FPGA). During implementation Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used rather than using embedded processors on the FPGA chip. The performance of the method is assessed according to the resources used in the FPGA chip on the development board and these results are also compared with the same approach without an interpolator.
{"title":"A novel command generation method with variable feedrate utilizing FGPA for motor drives","authors":"U. Yaman, M. Dolen, A. Koku","doi":"10.1109/WISES.2010.5548429","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548429","url":null,"abstract":"This paper focuses on a novel command generator for servo-motor drives to be used as an integral part of their motion controllers. The method, which incorporates a new data compression algorithm, is capable of generating trajectory data at variable rates. In this paradigm, higher-order differences of a given trajectory (i.e. position) are first computed and thus the resulting data are compressed via the proposed technique. The generation of the commands is carried out according to the feedrate (i.e. the speed along the trajectory) set by the external logic dynamically. The paper discusses the implementation of the method on a Field Programmable Gate Array (FPGA). During implementation Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used rather than using embedded processors on the FPGA chip. The performance of the method is assessed according to the resources used in the FPGA chip on the development board and these results are also compared with the same approach without an interpolator.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133949322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548929
N. Petrellis, M. Birbas, J. Kikidis, A. Birbas
An ultra low area 8-bit subrange Analogue/Digital Converter that consists of a pair of Flash 4-bit converter stages is described in this paper emphasising on the appropriate method for its real time calibration. Its active area occupies only 0.04 mm2 and dissipates less than 22 mW. The sampling rate is higher than 500 MS/s and the achieved Signal to Noise and Distortion Ratio is higher than 40 dB. A voltage mode integer divider is used at the input of this Analogue/Digital Converter driving the two output Flash stages by its quotient and residue. The ultra low area and power is owed to the use of the integer divider at the input stage of the subrange converter and the employment of a “thermometer to binary encoder” instead of a full 4-bit Flash Analogue/Digital Converter for the generation of the 4 most significant bits. The calibration method employed for this Analogue/Digital Converter is based on the proper biasing of the resistor ladders used by the fine 4-bit Flash stage as well as on properly delaying and shifting of the divider signals that generate the residue.
{"title":"Selecting appropriate calibration points for an ultra low area 8-bit subrange ADC","authors":"N. Petrellis, M. Birbas, J. Kikidis, A. Birbas","doi":"10.1109/WISES.2010.5548929","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548929","url":null,"abstract":"An ultra low area 8-bit subrange Analogue/Digital Converter that consists of a pair of Flash 4-bit converter stages is described in this paper emphasising on the appropriate method for its real time calibration. Its active area occupies only 0.04 mm2 and dissipates less than 22 mW. The sampling rate is higher than 500 MS/s and the achieved Signal to Noise and Distortion Ratio is higher than 40 dB. A voltage mode integer divider is used at the input of this Analogue/Digital Converter driving the two output Flash stages by its quotient and residue. The ultra low area and power is owed to the use of the integer divider at the input stage of the subrange converter and the employment of a “thermometer to binary encoder” instead of a full 4-bit Flash Analogue/Digital Converter for the generation of the 4 most significant bits. The calibration method employed for this Analogue/Digital Converter is based on the proper biasing of the resistor ladders used by the fine 4-bit Flash stage as well as on properly delaying and shifting of the divider signals that generate the residue.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128983259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548432
Kai Lutz, A. König
In the last decade, wireless sensor networks (WSN) have gained considerable importance and momentum. They are used with a growing diversity of sensors in a plethora of applications, e.g., from Ambient Intelligence (AmI), Assisted Living (AAL) to agriculture. WSN based measurement and instrumentation systems commonly have to operate under tight power consumption constraints. In particular, WSN benefiting from micro-electro-mechanical-system (MEMS) miniaturization have a very limited power budget due to poor energy density of storage elements. While highly optimized microcontrollers are available by now, today's sensors and sensor electronics are the predominant cause of power consumption in WSN. The standard approach tries to minimize standby currents by low-power sensor, bridge, and amplifier design. In contrast, this paper investigates an approach of duty-cycled, reconfigurable sensor electronics for resistive bridge sensors, that seamlessly integrates into microcontroller' sleep modes. The circuit is optimized for the particular case of anisotropic magneto-resistive (AMR) sensor based localization in autonomous WSN. In a systematic analysis amplifier currents, slew-rate, and read-out or on-time Ton are optimized for minimum power consumption of a tri-axial AMR sensor. At the required read-out rates, e.g., one measurement per minute, energy consumption can be reduced to a factor 1.5·10−6 of the continuous operation. A reconfigurable chip in a standard 0.35 µm bulk CMOS technology is under preparation adding flexibility for different sensor types and calibration needs.
{"title":"Minimizing power consumption in wireless sensor networks by duty-cycled reconfigurable sensor electronics","authors":"Kai Lutz, A. König","doi":"10.1109/WISES.2010.5548432","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548432","url":null,"abstract":"In the last decade, wireless sensor networks (WSN) have gained considerable importance and momentum. They are used with a growing diversity of sensors in a plethora of applications, e.g., from Ambient Intelligence (AmI), Assisted Living (AAL) to agriculture. WSN based measurement and instrumentation systems commonly have to operate under tight power consumption constraints. In particular, WSN benefiting from micro-electro-mechanical-system (MEMS) miniaturization have a very limited power budget due to poor energy density of storage elements. While highly optimized microcontrollers are available by now, today's sensors and sensor electronics are the predominant cause of power consumption in WSN. The standard approach tries to minimize standby currents by low-power sensor, bridge, and amplifier design. In contrast, this paper investigates an approach of duty-cycled, reconfigurable sensor electronics for resistive bridge sensors, that seamlessly integrates into microcontroller' sleep modes. The circuit is optimized for the particular case of anisotropic magneto-resistive (AMR) sensor based localization in autonomous WSN. In a systematic analysis amplifier currents, slew-rate, and read-out or on-time Ton are optimized for minimum power consumption of a tri-axial AMR sensor. At the required read-out rates, e.g., one measurement per minute, energy consumption can be reduced to a factor 1.5·10−6 of the continuous operation. A reconfigurable chip in a standard 0.35 µm bulk CMOS technology is under preparation adding flexibility for different sensor types and calibration needs.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125402502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548435
A. Meliones
The term embedded systems refers to digital systems including hardware and software co-development for special applications, the most common being networking and control. Because of their individual architecture, their hardware and software development is quite often a very complicated process. Embedded systems involve a wide spectrum of specializations, such as system architecture design, hardware design, operating system porting, device driver programming, and application development. The focus of this paper is on the understanding of embedded systems architecture and development methodology with emphasis on network embedded systems.
{"title":"A comprehensive development guide for network embedded systems","authors":"A. Meliones","doi":"10.1109/WISES.2010.5548435","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548435","url":null,"abstract":"The term embedded systems refers to digital systems including hardware and software co-development for special applications, the most common being networking and control. Because of their individual architecture, their hardware and software development is quite often a very complicated process. Embedded systems involve a wide spectrum of specializations, such as system architecture design, hardware design, operating system porting, device driver programming, and application development. The focus of this paper is on the understanding of embedded systems architecture and development methodology with emphasis on network embedded systems.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"13 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114913241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548428
Alessio Ercole De Stephanis, M. Conti, M. Caldari, F. Ripa
A fundamental issue in the development of a modern electronic design is represented by productivity: the complexity of digital systems is growing so fast that a lot of resources are required for meaningful and efficient design, guaranteeing a feasible time-to-market. Abstraction is an important tool to manage complexity, because it allows to catch the essence of an object, giving less importance to other properties, avoiding premature introduction of implementation details. For this reason it is important to adopt a methodology that can lead to the desired functionality through the creation of high-level executable models that can be easily refined and adapted to the subsequent stages of hardware and software synthesis. In this paper, this methodology is applied in the development of an audio dynamic range compressor designed for the creation of an electronic musical keyboard.
{"title":"Design refinement for the development of an audio dynamic range controller","authors":"Alessio Ercole De Stephanis, M. Conti, M. Caldari, F. Ripa","doi":"10.1109/WISES.2010.5548428","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548428","url":null,"abstract":"A fundamental issue in the development of a modern electronic design is represented by productivity: the complexity of digital systems is growing so fast that a lot of resources are required for meaningful and efficient design, guaranteeing a feasible time-to-market. Abstraction is an important tool to manage complexity, because it allows to catch the essence of an object, giving less importance to other properties, avoiding premature introduction of implementation details. For this reason it is important to adopt a methodology that can lead to the desired functionality through the creation of high-level executable models that can be easily refined and adapted to the subsequent stages of hardware and software synthesis. In this paper, this methodology is applied in the development of an audio dynamic range compressor designed for the creation of an electronic musical keyboard.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133162742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548425
Bhuvana Kakunoori, Sreekumar Choyar Madathil
In the present paper, we propose a mechanism to support dynamic task scheduling on multiprocessor systems, which assists the scheduler in efficiently and adaptively managing the platform resources. The main objective of this method is to maximize system resource utilization, by allocating available platform resources to a task based on the individual task characteristics and performance requirements.
{"title":"Hardware support for dynamic scheduling in multiprocessor Operating System","authors":"Bhuvana Kakunoori, Sreekumar Choyar Madathil","doi":"10.1109/WISES.2010.5548425","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548425","url":null,"abstract":"In the present paper, we propose a mechanism to support dynamic task scheduling on multiprocessor systems, which assists the scheduler in efficiently and adaptively managing the platform resources. The main objective of this method is to maximize system resource utilization, by allocating available platform resources to a task based on the individual task characteristics and performance requirements.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122377466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548423
Pieretti Andrea, Cristiano Scavongelli, S. Orcioni, M. Conti
This paper presents a performance analysis of JPEG 2000 image compression over a 802.15.4 wireless network. The interdependence among image quality, JPEG 2000 compression parameters and network throughput have been investigated. The objective of the work is to give useful guidelines in the design of image wireless networks over low cost, low power, low rate 802.15.4 wireless protocol.
{"title":"Performance analysis of JPEG 2000 over 802.15.4 wireless image sensor network","authors":"Pieretti Andrea, Cristiano Scavongelli, S. Orcioni, M. Conti","doi":"10.1109/WISES.2010.5548423","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548423","url":null,"abstract":"This paper presents a performance analysis of JPEG 2000 image compression over a 802.15.4 wireless network. The interdependence among image quality, JPEG 2000 compression parameters and network throughput have been investigated. The objective of the work is to give useful guidelines in the design of image wireless networks over low cost, low power, low rate 802.15.4 wireless protocol.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126401877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548426
J. Fernández, R. Seepold, J. Augusto, N. M. Madrid
Decision-making for trading requires a complex infrastructure: technical analysis, fundamental analysis, expert systems indicating propitious moments of operation, and more. However, one very relevant element is usually underestimated: a trader's stress level, which can significantly undermine the trader's capability to think clearly. This paper explains how stress information can be gathered from sensors during a trading operation, which sensors can be used for this purpose, and proposes a decision-making process supported by measuring stress through sensors which can lead to a Stress—Aware Trader.
{"title":"Sensors in trading process: A Stress—Aware Trader","authors":"J. Fernández, R. Seepold, J. Augusto, N. M. Madrid","doi":"10.1109/WISES.2010.5548426","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548426","url":null,"abstract":"Decision-making for trading requires a complex infrastructure: technical analysis, fundamental analysis, expert systems indicating propitious moments of operation, and more. However, one very relevant element is usually underestimated: a trader's stress level, which can significantly undermine the trader's capability to think clearly. This paper explains how stress information can be gathered from sensors during a trading operation, which sensors can be used for this purpose, and proposes a decision-making process supported by measuring stress through sensors which can lead to a Stress—Aware Trader.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122503755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-08DOI: 10.1109/WISES.2010.5548438
Jussi Kiljander, Matti Eteläperä, Janne Takalo-Mattila, J. Soininen
Smart Spaces are an emerging computing paradigm in which various devices of our everyday environment share information autonomously with each other in order to provide services to people in the environment. Achieving reliable way to share information between heterogeneous devices is not an easy process however. Solutions that are independent of application domain and that provide interoperability for the devices of the Smart Space are needed. This paper presents a new application domain independent approach for low capacity embedded systems to be part of applications and use cases based on semantic information interoperability. The approach uses NoTA and Smart-M3 solutions to open embedded information for devices in the Smart Space. A reference implementation of smart greenhouse is used to demonstrate the approach in practice.
{"title":"Opening information of low capacity embedded systems for Smart Spaces","authors":"Jussi Kiljander, Matti Eteläperä, Janne Takalo-Mattila, J. Soininen","doi":"10.1109/WISES.2010.5548438","DOIUrl":"https://doi.org/10.1109/WISES.2010.5548438","url":null,"abstract":"Smart Spaces are an emerging computing paradigm in which various devices of our everyday environment share information autonomously with each other in order to provide services to people in the environment. Achieving reliable way to share information between heterogeneous devices is not an easy process however. Solutions that are independent of application domain and that provide interoperability for the devices of the Smart Space are needed. This paper presents a new application domain independent approach for low capacity embedded systems to be part of applications and use cases based on semantic information interoperability. The approach uses NoTA and Smart-M3 solutions to open embedded information for devices in the Smart Space. A reference implementation of smart greenhouse is used to demonstrate the approach in practice.","PeriodicalId":166416,"journal":{"name":"2010 8th Workshop on Intelligent Solutions in Embedded Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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