Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159293
G. Taylor
Hardware for radix four division and radix two square root is shared in a processor designed to implement the proposed IEEE floating-point standard. The division hardware looks ahead to find the next quotient digit in parallel with the next partial remainder. An 8-bit ALU estimates the next remainder's leading bits. The quotient digit look-up table is addressed with a truncation of the estimate rather than a truncation of the full partial remainder. The estimation ALU and the look-up table are asymmetric for positive and negative remainders. This asymmetry reduces the width of the ALU and the number of minterms in the logic equations for thy look-up table. The square root algorithm obtains the correctly rounded result in about two division times using small extensions to the division hardware.
{"title":"Compatible hardware for division and square root","authors":"G. Taylor","doi":"10.1109/ARITH.1981.6159293","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159293","url":null,"abstract":"Hardware for radix four division and radix two square root is shared in a processor designed to implement the proposed IEEE floating-point standard. The division hardware looks ahead to find the next quotient digit in parallel with the next partial remainder. An 8-bit ALU estimates the next remainder's leading bits. The quotient digit look-up table is addressed with a truncation of the estimate rather than a truncation of the full partial remainder. The estimation ALU and the look-up table are asymmetric for positive and negative remainders. This asymmetry reduces the width of the ALU and the number of minterms in the logic equations for thy look-up table. The square root algorithm obtains the correctly rounded result in about two division times using small extensions to the division hardware.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132938655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159287
Hong Peng
This paper describes a kind of algorithms for fast extracting square roots and cube roots, their mathematical proofs, their revised algorithm formulae, and hardware implementation of the square root algorithm. These algorithms may be of no significance for large scale computer with fast division. But I am sure that it is effective and economical to apply these algorithms to the circuit designs of some mini- and microcomputers with general multiplication and division, such as nonrestoring division.
{"title":"Algorithms for extracting square roots and cube roots","authors":"Hong Peng","doi":"10.1109/ARITH.1981.6159287","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159287","url":null,"abstract":"This paper describes a kind of algorithms for fast extracting square roots and cube roots, their mathematical proofs, their revised algorithm formulae, and hardware implementation of the square root algorithm. These algorithms may be of no significance for large scale computer with fast division. But I am sure that it is effective and economical to apply these algorithms to the circuit designs of some mini- and microcomputers with general multiplication and division, such as nonrestoring division.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134531583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159273
A. Gorji-Sinaki, M. Ercegovac
A gate level design of a digit-slice on-line arithmetic unit is presented. This unit is designed as a set of basic modules, Processing Elements (PE), each of which operates on a single digit of the operands and the results. It is capable of executing four basic operations of addition/subtraction, multiplication and division in an on-line manner. The results are generated during the digit-serial input of the operands, beginning always with the most significant digit. A general (with respect to radix) analysis of the cost and speed of the proposed unit is also given.
{"title":"Design of a digit-slice on-line arithmetic unit","authors":"A. Gorji-Sinaki, M. Ercegovac","doi":"10.1109/ARITH.1981.6159273","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159273","url":null,"abstract":"A gate level design of a digit-slice on-line arithmetic unit is presented. This unit is designed as a set of basic modules, Processing Elements (PE), each of which operates on a single digit of the operands and the results. It is capable of executing four basic operations of addition/subtraction, multiplication and division in an on-line manner. The results are generated during the digit-serial input of the operands, beginning always with the most significant digit. A general (with respect to radix) analysis of the cost and speed of the proposed unit is also given.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130196033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159292
Rob A. Rutenbar, Y. E. Park
We present a case study of the application of recently evolved structured VLSI design methodologies to the design and implementation of a simple VLSI quasi-serial inner product machine.
{"title":"Case study of a VLSI design project: A simple inner product machine","authors":"Rob A. Rutenbar, Y. E. Park","doi":"10.1109/ARITH.1981.6159292","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159292","url":null,"abstract":"We present a case study of the application of recently evolved structured VLSI design methodologies to the design and implementation of a simple VLSI quasi-serial inner product machine.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"359 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159286
C. Papachristou
This paper presents two related algorithms for implementing parallel n-bit binary addition and evaluating n-th degree polynomials, respectively. The approach taken makes use of an iterative construction, the computation tree. The algorithms are particularly effective for moderate values of n and are in accord with well-known asymptotic bounds. In the case of n-bit addition, the implementations constitute look-ahead tree circuits of r-input standard logic elements. Extensions to modular tree structures for lookahead adders are also considered. In the case of parallel polynomial evaluation, the operations of ordinary addition and multiplication are assumed with the capability to employ r arguments simultaneously.
{"title":"Algorithms for parallel addition and parallel polynomial evaluation","authors":"C. Papachristou","doi":"10.1109/ARITH.1981.6159286","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159286","url":null,"abstract":"This paper presents two related algorithms for implementing parallel n-bit binary addition and evaluating n-th degree polynomials, respectively. The approach taken makes use of an iterative construction, the computation tree. The algorithms are particularly effective for moderate values of n and are in accord with well-known asymptotic bounds. In the case of n-bit addition, the implementations constitute look-ahead tree circuits of r-input standard logic elements. Extensions to modular tree structures for lookahead adders are also considered. In the case of parallel polynomial evaluation, the operations of ordinary addition and multiplication are assumed with the capability to employ r arguments simultaneously.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127543464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159295
Gregory Walker
The synthetic aspect of designing a computer architecture is particularly evident when the design is highly constrained from two independent directions. Floating-point extensions of the MC68000 architecture incorporate the IEEE Proposed Floating-point Standard into the existing MC68000 architecture.
{"title":"Extension of the MC68000 architecture to include Standard Floating-point arithmetic","authors":"Gregory Walker","doi":"10.1109/ARITH.1981.6159295","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159295","url":null,"abstract":"The synthetic aspect of designing a computer architecture is particularly evident when the design is highly constrained from two independent directions. Floating-point extensions of the MC68000 architecture incorporate the IEEE Proposed Floating-point Standard into the existing MC68000 architecture.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120979473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159275
R. T. Gregory
A method is described for doing residue arithmetic when the operands are rational numbers. A rational operand a/b is mapped onto the integer |a·b−1|p and the arithmetic is performed in GF(p). A method is given for taking an integer result and finding its rational equivalent (the one which corresponds to the correct rational result).
{"title":"Residue arithmetic with rational operands","authors":"R. T. Gregory","doi":"10.1109/ARITH.1981.6159275","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159275","url":null,"abstract":"A method is described for doing residue arithmetic when the operands are rational numbers. A rational operand a/b is mapped onto the integer |a·b<sup>−1</sup>|<inf>p</inf> and the arithmetic is performed in GF(p). A method is given for taking an integer result and finding its rational equivalent (the one which corresponds to the correct rational result).","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128812837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159282
S. Markov
It is our point of view that familiar interval arithmetic defined by A∗B={a ∗ b: a ∊ A, b ∊ B}, ∗ ∊{+, −, ×, :} is inefficient in certain respects. For instance, it is not in a position to produce exact representations, of sets of the form {f(x, y, …, z):x ∊ X, y ∊ Y, …, z ∊ Z} even for simple functions f of one variable. We make use of another interval arithmetic which is very convenient for computer computations and for construction of interval algorithms. As an example we consider a method for the construction of interval expressions for sets of the form if {f(x):x ∊[x1, x2]}, where f is an elementary function.
我们认为由A∗B={A∗B: A A, B B}，∗{+，−，x，:}所定义的区间算法在某些方面是无效的。例如，即使对于单变量的简单函数f，也不能给出{f(x, y，…，z):x x, y y，…，z z}的集合的精确表示。我们利用了另一种区间算法，它对计算机计算和区间算法的构造都非常方便。作为一个例子，我们考虑一种构造形式为if {f(x):x [x1, x2]}的集合的区间表达式的方法，其中f是初等函数。
{"title":"On an interval arithmetic and its applications","authors":"S. Markov","doi":"10.1109/ARITH.1981.6159282","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159282","url":null,"abstract":"It is our point of view that familiar interval arithmetic defined by A∗B={a ∗ b: a ∊ A, b ∊ B}, ∗ ∊{+, −, ×, :} is inefficient in certain respects. For instance, it is not in a position to produce exact representations, of sets of the form {f(x, y, …, z):x ∊ X, y ∊ Y, …, z ∊ Z} even for simple functions f of one variable. We make use of another interval arithmetic which is very convenient for computer computations and for construction of interval algorithms. As an example we consider a method for the construction of interval expressions for sets of the form if {f(x):x ∊[x<inf>1</inf>, x<inf>2</inf>]}, where f is an elementary function.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133269295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159298
Robert Willoner, I. Chen
The best known algorithm for modular exponentiation Me mod t for arbitrary M, e and t is of O(n3) where n is the number of bits in the largest of M, e and t. This paper presents an O(n2) algorithm for the problem where Me mod t is required for many values of M and e with constant t some preprocessing is done on t, and the results are applied repeatedly to different values of M and e. The main algorithm involves on-line arithmetic in a redundant. number system. An immediate application is in encoding/decoding of messages in an RSA-based public-key cryptosystem.
最著名的模幂运算算法我国防部为任意M t, e和t O (n3),其中n是最大的的比特数M, e和t。本文提出了一种O (n2)算法的问题,我国防部t需要许多的M和e值常数t一些预处理完成,并且结果是反复适用于不同的M值和e。涉及到的主要算法在线冗余运算。数字系统。即时应用程序是在基于rsa的公钥密码系统中对消息进行编码/解码。
{"title":"An algorithm for modular exponentiation","authors":"Robert Willoner, I. Chen","doi":"10.1109/ARITH.1981.6159298","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159298","url":null,"abstract":"The best known algorithm for modular exponentiation Me mod t for arbitrary M, e and t is of O(n3) where n is the number of bits in the largest of M, e and t. This paper presents an O(n2) algorithm for the problem where Me mod t is required for many values of M and e with constant t some preprocessing is done on t, and the results are applied repeatedly to different values of M and e. The main algorithm involves on-line arithmetic in a redundant. number system. An immediate application is in encoding/decoding of messages in an RSA-based public-key cryptosystem.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131364169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159278
Saroj Kaushik, R. Arora
This paper is concerned with the algebraic sign detection of a number in the Symmetric Residue Number System, A new approach has been suggested which completely avoid the time consuming process of the Symmetric Mixed Radix Conversion (SMRC). An algorithm based on the above approach implementable in parallel for sign detection is also presented. The heriware representation of the above algorithm is shown. The time and hardware complexity required for the process have also bean computed.
{"title":"Sign detection in the Symmetric Residue Number System","authors":"Saroj Kaushik, R. Arora","doi":"10.1109/ARITH.1981.6159278","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159278","url":null,"abstract":"This paper is concerned with the algebraic sign detection of a number in the Symmetric Residue Number System, A new approach has been suggested which completely avoid the time consuming process of the Symmetric Mixed Radix Conversion (SMRC). An algorithm based on the above approach implementable in parallel for sign detection is also presented. The heriware representation of the above algorithm is shown. The time and hardware complexity required for the process have also bean computed.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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