Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159274
J. Gosling, J. Zurawski, D. Edwards
Although the advent of microprocessors has put considerable computing power in the hands of large numbers of users, there is still an important group who have yet to benefit fully from large scale integration. As a step in the direction of rectifying this situation, a highly flexible chip set is being designed, with a view to reducing the cost of a powerful floating point processor by a factor of about 4. Processing speed will be up to twice that of an equivalent unit built from MSI devices, before allowance is made for savings on wiring delays. It will be possible to construct a unit satisfying all published standards, proposed and existing (de facto), as well as permitting a number of extensions not specifically in these standards. At a cost between 100 and 150 ICs, and with a floating-point add time of around 120nS, the proposed unit is cost-effective compared to currently available coprocessors.
{"title":"A chip-set for a high-speed low-cost floating-point unit","authors":"J. Gosling, J. Zurawski, D. Edwards","doi":"10.1109/ARITH.1981.6159274","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159274","url":null,"abstract":"Although the advent of microprocessors has put considerable computing power in the hands of large numbers of users, there is still an important group who have yet to benefit fully from large scale integration. As a step in the direction of rectifying this situation, a highly flexible chip set is being designed, with a view to reducing the cost of a powerful floating point processor by a factor of about 4. Processing speed will be up to twice that of an equivalent unit built from MSI devices, before allowance is made for savings on wiring delays. It will be possible to construct a unit satisfying all published standards, proposed and existing (de facto), as well as permitting a number of extensions not specifically in these standards. At a cost between 100 and 150 ICs, and with a floating-point add time of around 120nS, the proposed unit is cost-effective compared to currently available coprocessors.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121654403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159296
O. Watanuki, M. Ercegovac
For effective application of on-line arithmetic to practical numerical problems, floating-point algorithms for on-line addition/subtraction and multiplication have been implemented by introducing the notion of quasi-normalization. Those proposed are normalized fixed-precision FLPOL (floating-point on-line) algorithms.
{"title":"Floating-point on-line arithmetic: Algorithms","authors":"O. Watanuki, M. Ercegovac","doi":"10.1109/ARITH.1981.6159296","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159296","url":null,"abstract":"For effective application of on-line arithmetic to practical numerical problems, floating-point algorithms for on-line addition/subtraction and multiplication have been implemented by introducing the notion of quasi-normalization. Those proposed are normalized fixed-precision FLPOL (floating-point on-line) algorithms.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121076322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159281
P. Ligomenides, R. Newcomb
Two complement representations and a sign-magnitude one are introduced which allow for handling negative numbers using only binary coefficients in Fibonacci base expansions. These are developed for practical implementation in Fibonacci computers.
{"title":"Complement representations in the Fibonacci computer","authors":"P. Ligomenides, R. Newcomb","doi":"10.1109/ARITH.1981.6159281","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159281","url":null,"abstract":"Two complement representations and a sign-magnitude one are introduced which allow for handling negative numbers using only binary coefficients in Fibonacci base expansions. These are developed for practical implementation in Fibonacci computers.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128827065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159280
Peter Kornerup, D. Matula
Based on the classical Euclidian Algorithm, we develop the foundations of an arithmetic unit performing Add, Subtract, Multiply and Divide on rational operands. The unit uses one unified algorithm for all operations, including rounding. A binary implementation, based on techniques known from the SRT division, is described. Finally, a hardware implementation using ripple-free, carry-save addition is analyzed, and adapted to a floating-slash representation of the rational operands.
{"title":"An integrated rational arithmetic unit","authors":"Peter Kornerup, D. Matula","doi":"10.1109/ARITH.1981.6159280","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159280","url":null,"abstract":"Based on the classical Euclidian Algorithm, we develop the foundations of an arithmetic unit performing Add, Subtract, Multiply and Divide on rational operands. The unit uses one unified algorithm for all operations, including rounding. A binary implementation, based on techniques known from the SRT division, is described. Finally, a hardware implementation using ripple-free, carry-save addition is analyzed, and adapted to a floating-slash representation of the rational operands.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121965340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159288
C. Raghavendra, M. Ercegovac
On-line arithmetic is a special class of serial arithmetic where algorithms produce results with the most significant digit first during the serial input of the operands. Speedup of computations can be achieved by overlapping or pipelining successive operations with small delays. This paper describes the design and implementation of a simulator for on-line arithmetic algorithms. The simulator was designed primarily to serve as 1) an experimental tool for synthesis of on-line algorithms; 2) a performance evaluation tool of on-line arithmetic; 3) an on-line calculator in solving some problems involving linear and non-linear recurrences. The simulator evaluates arithmetic expressions given in a highly functional form. Presently, the set of operations supported include addition, subtraction, multiplication, division, and square root. Several examples are presented in this paper to illustrate the usage of the simulator. The simulator package is implemented in ‘C’ language on a VAX 11/780 system.
{"title":"A simulator for on-line arithmetic","authors":"C. Raghavendra, M. Ercegovac","doi":"10.1109/ARITH.1981.6159288","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159288","url":null,"abstract":"On-line arithmetic is a special class of serial arithmetic where algorithms produce results with the most significant digit first during the serial input of the operands. Speedup of computations can be achieved by overlapping or pipelining successive operations with small delays. This paper describes the design and implementation of a simulator for on-line arithmetic algorithms. The simulator was designed primarily to serve as 1) an experimental tool for synthesis of on-line algorithms; 2) a performance evaluation tool of on-line arithmetic; 3) an on-line calculator in solving some problems involving linear and non-linear recurrences. The simulator evaluates arithmetic expressions given in a highly functional form. Presently, the set of operations supported include addition, subtraction, multiplication, division, and square root. Several examples are presented in this paper to illustrate the usage of the simulator. The simulator package is implemented in ‘C’ language on a VAX 11/780 system.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132570720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1981-05-16DOI: 10.1109/ARITH.1981.6159284
S. Ong, D. Atkins
This paper describes an evolving Arithmetic Design System (ADS) to support the quantitative evaluation of alternate number systems with respect to a given application and realization technology. In computer arithmetic we are concerned with establishing a correspondence between abstract quantities (numbers) and some physical representation (symbols), and with simulating the operations on these symbols. The ADS is intended to help study the cost and performance of alternate simulations. A finite number system is a triple consisting of a symbol set (elements are called "digit-vectors"), an interpretation set, a mapping between these two sets, and a set of operators (digit-vector algorithms) defined on its symbol set. A set of these digit vector algorithms are proposed for conducting arithmetic design. A number system matrix defines the digit vector algorithm for numerous number systems and a method for computing time and space complexity of compositions of these algorithms is proposed. An example of how the system could be used to compare addition, with and without overflow detection, for three number systems is given.
{"title":"Towards quantitative comparison of computer number systems","authors":"S. Ong, D. Atkins","doi":"10.1109/ARITH.1981.6159284","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159284","url":null,"abstract":"This paper describes an evolving Arithmetic Design System (ADS) to support the quantitative evaluation of alternate number systems with respect to a given application and realization technology. In computer arithmetic we are concerned with establishing a correspondence between abstract quantities (numbers) and some physical representation (symbols), and with simulating the operations on these symbols. The ADS is intended to help study the cost and performance of alternate simulations. A finite number system is a triple consisting of a symbol set (elements are called \"digit-vectors\"), an interpretation set, a mapping between these two sets, and a set of operators (digit-vector algorithms) defined on its symbol set. A set of these digit vector algorithms are proposed for conducting arithmetic design. A number system matrix defines the digit vector algorithm for numerous number systems and a method for computing time and space complexity of compositions of these algorithms is proposed. An example of how the system could be used to compare addition, with and without overflow detection, for three number systems is given.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126511744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ARITH.1981.6159290
T. Rao, R. T. Gregory
In a finite-segment p-adic number system one of the difficult problems is concerned with converting Hensel codes back into rational numbers. An algorithm for this conversion is proposed which is based on a sophisticated table look-up procedure.
{"title":"The conversion of Hensel codes to rational numbers","authors":"T. Rao, R. T. Gregory","doi":"10.1109/ARITH.1981.6159290","DOIUrl":"https://doi.org/10.1109/ARITH.1981.6159290","url":null,"abstract":"In a finite-segment p-adic number system one of the difficult problems is concerned with converting Hensel codes back into rational numbers. An algorithm for this conversion is proposed which is based on a sophisticated table look-up procedure.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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