Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00131
B. Shrestha, Richard Cziva, Engin Arslan
Edge computing promises low-latency computation for delay sensitive applications by processing data close to its source. Task scheduling in edge computing is however not immune to performance fluctuations as dynamic and unpredictable nature of network traffic can adversely affect the data transfer performance between end devices and edge servers. In this paper, we leverage In-band Network Telemetry (INT) to gather fine-grained, temporal statistics about network conditions and incorporate network-awareness into task scheduling for edge computing. Unlike legacy network monitoring techniques that collect port-level or flow-level statistics at the order of tens of seconds, INT offers highly accurate network visibility by capturing network telemetry at packet-level granularity, thereby presenting a unique opportunity to detect network congestion precisely. Our experimental analysis using various workload types and network congestion scenarios reveal that enhancing task scheduling of edge computing with high-precision network telemetry can lead up to 40% reduction in data transfer times and up to 30% reduction in total task execution times by favoring edge servers in uncongested (or mildly congested) sections of network when scheduling tasks.
{"title":"INT Based Network-Aware Task Scheduling for Edge Computing","authors":"B. Shrestha, Richard Cziva, Engin Arslan","doi":"10.1109/IPDPSW52791.2021.00131","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00131","url":null,"abstract":"Edge computing promises low-latency computation for delay sensitive applications by processing data close to its source. Task scheduling in edge computing is however not immune to performance fluctuations as dynamic and unpredictable nature of network traffic can adversely affect the data transfer performance between end devices and edge servers. In this paper, we leverage In-band Network Telemetry (INT) to gather fine-grained, temporal statistics about network conditions and incorporate network-awareness into task scheduling for edge computing. Unlike legacy network monitoring techniques that collect port-level or flow-level statistics at the order of tens of seconds, INT offers highly accurate network visibility by capturing network telemetry at packet-level granularity, thereby presenting a unique opportunity to detect network congestion precisely. Our experimental analysis using various workload types and network congestion scenarios reveal that enhancing task scheduling of edge computing with high-precision network telemetry can lead up to 40% reduction in data transfer times and up to 30% reduction in total task execution times by favoring edge servers in uncongested (or mildly congested) sections of network when scheduling tasks.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115690623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ipdpsw52791.2021.00063
{"title":"Message from the HIPS 2021 Workshop Co-Chairs","authors":"","doi":"10.1109/ipdpsw52791.2021.00063","DOIUrl":"https://doi.org/10.1109/ipdpsw52791.2021.00063","url":null,"abstract":"","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127152278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00114
K. Nakajima, T. Ogita, Masatoshi Kawai
The parallel multigrid method is expected to play an important role in scientific computing on exa-scale supercomputer systems for solving large-scale linear equations with sparse coefficient matrices. Because solving sparse linear systems is a very memory-bound process, efficient method for storage of coefficient matrices is a crucial issue. In the previous works, authors implemented sliced ELL method to parallel conjugate gradient solvers with multigrid preconditioning (MGCG) for the application on 3D groundwater flow through heterogeneous porous media (pGW3D-LVM), and excellent performance has been obtained on large-scale multicore/manycore clusters. In the present work, authors introduced SELL-C-σ with double/single precision computing to the MGCG solver, and evaluated the performance of the solver with OpenMP/MPI hybrid parallel programing models on the Oakforest-PACS (OLP) system at JCAHPC using up to 2,048 nodes of Intel Xeon Phi. Because SELL-C-σ is suitable for wide-SIMD architecture, such as Xeon Phi, improvement of the performance over the sliced ELL was more than 35% for double precision and more than 45% for single precision on OFP. Finally, accuracy verification was conducted based on the method proposed by authors for solving linear equations with sparse coefficient matrices with M-property.
{"title":"Efficient Parallel Multigrid Methods on Manycore Clusters with Double/Single Precision Computing","authors":"K. Nakajima, T. Ogita, Masatoshi Kawai","doi":"10.1109/IPDPSW52791.2021.00114","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00114","url":null,"abstract":"The parallel multigrid method is expected to play an important role in scientific computing on exa-scale supercomputer systems for solving large-scale linear equations with sparse coefficient matrices. Because solving sparse linear systems is a very memory-bound process, efficient method for storage of coefficient matrices is a crucial issue. In the previous works, authors implemented sliced ELL method to parallel conjugate gradient solvers with multigrid preconditioning (MGCG) for the application on 3D groundwater flow through heterogeneous porous media (pGW3D-LVM), and excellent performance has been obtained on large-scale multicore/manycore clusters. In the present work, authors introduced SELL-C-σ with double/single precision computing to the MGCG solver, and evaluated the performance of the solver with OpenMP/MPI hybrid parallel programing models on the Oakforest-PACS (OLP) system at JCAHPC using up to 2,048 nodes of Intel Xeon Phi. Because SELL-C-σ is suitable for wide-SIMD architecture, such as Xeon Phi, improvement of the performance over the sliced ELL was more than 35% for double precision and more than 45% for single precision on OFP. Finally, accuracy verification was conducted based on the method proposed by authors for solving linear equations with sparse coefficient matrices with M-property.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127195388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ipdpsw52791.2021.00148
{"title":"Message from the HPS 2021 Workshop Chairs","authors":"","doi":"10.1109/ipdpsw52791.2021.00148","DOIUrl":"https://doi.org/10.1109/ipdpsw52791.2021.00148","url":null,"abstract":"","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126952554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00116
Kou Murakami, K. Komatsu, Masayuki Sato, Hiroaki Kobayashi
In recent years, machine learning has become widespread. Since machine learning algorithms have become complex and the amount of data to be handled have become large, the execution times of machine learning programs have been increasing. Processors called accelerators can contribute to the execution of a machine learning program with a short time. However, the processors including the accelerators have different characteristics. Therefore, it is unclear whether existing machine learning programs are executed on the appropriate processor or not. This paper proposes a method for selecting a processor suitable for each machine learning program. In the proposed method, the selection is based on the estimation of the execution time of machine learning programs on each processor. The proposed method does not need to execute a target machine learning program in advance. From the experimental results, it is clarified that the proposed method can achieve up to 5.3 times faster execution than the original implementation by NumPy. These results prove that the proposed method can be used in a system that automatically selects the processor so that each machine learning program can be easily executed on the best processor.
{"title":"A Processor Selection Method based on Execution Time Estimation for Machine Learning Programs","authors":"Kou Murakami, K. Komatsu, Masayuki Sato, Hiroaki Kobayashi","doi":"10.1109/IPDPSW52791.2021.00116","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00116","url":null,"abstract":"In recent years, machine learning has become widespread. Since machine learning algorithms have become complex and the amount of data to be handled have become large, the execution times of machine learning programs have been increasing. Processors called accelerators can contribute to the execution of a machine learning program with a short time. However, the processors including the accelerators have different characteristics. Therefore, it is unclear whether existing machine learning programs are executed on the appropriate processor or not. This paper proposes a method for selecting a processor suitable for each machine learning program. In the proposed method, the selection is based on the estimation of the execution time of machine learning programs on each processor. The proposed method does not need to execute a target machine learning program in advance. From the experimental results, it is clarified that the proposed method can achieve up to 5.3 times faster execution than the original implementation by NumPy. These results prove that the proposed method can be used in a system that automatically selects the processor so that each machine learning program can be easily executed on the best processor.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114593971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00035
Jianyu Chen, M.A.F.M. Daverveldt, Z. Al-Ars
With the continued increase in the amount of big data generated and stored in various application domains, such as high-frequency trading, compression techniques are becoming ever more important to reduce the requirements on communication bandwidth and storage capacity. Zstandard (Zstd) is emerging as an important compression algorithm for big data sets capable of achieving a good compression ratio but with a higher speed than comparable algorithms. In this paper, we introduce the architecture of a new hardware compression kernel for Zstd that allows the algorithm to be used for real-time compression of big data streams. In addition, we optimize the proposed architecture for the specific use case of streaming high-frequency trading data. The optimized kernel is implemented on a Xilinx Alveo U200 board. Our optimized implementation allows us to fit ten kernel blocks on one board, which is able to achieve a compression throughput of about 8.6GB/s and compression ratio of about 23.6%. The hardware implementation is open source and publicly available at https://github.com/ChenJianyunp/Hardware-Zstd-Compression-Unit.
{"title":"FPGA Acceleration of Zstd Compression Algorithm","authors":"Jianyu Chen, M.A.F.M. Daverveldt, Z. Al-Ars","doi":"10.1109/IPDPSW52791.2021.00035","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00035","url":null,"abstract":"With the continued increase in the amount of big data generated and stored in various application domains, such as high-frequency trading, compression techniques are becoming ever more important to reduce the requirements on communication bandwidth and storage capacity. Zstandard (Zstd) is emerging as an important compression algorithm for big data sets capable of achieving a good compression ratio but with a higher speed than comparable algorithms. In this paper, we introduce the architecture of a new hardware compression kernel for Zstd that allows the algorithm to be used for real-time compression of big data streams. In addition, we optimize the proposed architecture for the specific use case of streaming high-frequency trading data. The optimized kernel is implemented on a Xilinx Alveo U200 board. Our optimized implementation allows us to fit ten kernel blocks on one board, which is able to achieve a compression throughput of about 8.6GB/s and compression ratio of about 23.6%. The hardware implementation is open source and publicly available at https://github.com/ChenJianyunp/Hardware-Zstd-Compression-Unit.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116753781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00026
T. Martin, G. Grewal, S. Areibi
Timing-driven placement tools for FPGAs rely on the availability of accurate delay estimates for nets in order to identify and optimize critical paths. In this paper, we propose a machine-learning framework for predicting net delay to reduce miscorrelation between placement and detailed-routing. Features relevant to timing delay are engineered based on characteristics of nets, available routing resources, and the behavior of the detailed router. Our results show an accuracy above 94%, and when integrated within an FPGA analytical placer Critical Path Delay (CPD) is improved by 10% on average compared to a static delay model.
{"title":"A Machine Learning Approach to Predict Timing Delays During FPGA Placement","authors":"T. Martin, G. Grewal, S. Areibi","doi":"10.1109/IPDPSW52791.2021.00026","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00026","url":null,"abstract":"Timing-driven placement tools for FPGAs rely on the availability of accurate delay estimates for nets in order to identify and optimize critical paths. In this paper, we propose a machine-learning framework for predicting net delay to reduce miscorrelation between placement and detailed-routing. Features relevant to timing delay are engineered based on characteristics of nets, available routing resources, and the behavior of the detailed router. Our results show an accuracy above 94%, and when integrated within an FPGA analytical placer Critical Path Delay (CPD) is improved by 10% on average compared to a static delay model.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130353229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00084
Oswaldo Artiles, F. Saeed
Graphs that are used for modeling of human brain, omics data, or social networks are huge, and manual inspection of these graph is impossible. A popular, and fundamental, method used for making sense of these large graphs is the well-known Breadth-First Search (BFS) algorithm. However, BFS suffers from large computational cost especially for big graphs of interest. More recently, the use of Graphics processing units (GPU) has been promising, but challenging because of limited global memory of GPU’s, and irregular structures of real-world graphs. In this paper, we present a GPU based linear-algebraic formulation and implementation of BFS, called TurboBFS, that exhibits excellent scalability on unweighted, undirected or directed sparse graphs of arbitrary structure. We demonstrate that our algorithms obtain up to 40 GTEPs, and are on average 15.7x, 5.8x, and 1.8x faster than the other state-of-the-art algorithms implemented on the SuiteSparse:GraphBLAS, GraphBLAST, and gunrock libraries respectively. The codes to implement the algorithms proposed in this paper are available at https://github.com/pcdslab.
{"title":"TurboBFS: GPU Based Breadth-First Search (BFS) Algorithms in the Language of Linear Algebra","authors":"Oswaldo Artiles, F. Saeed","doi":"10.1109/IPDPSW52791.2021.00084","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00084","url":null,"abstract":"Graphs that are used for modeling of human brain, omics data, or social networks are huge, and manual inspection of these graph is impossible. A popular, and fundamental, method used for making sense of these large graphs is the well-known Breadth-First Search (BFS) algorithm. However, BFS suffers from large computational cost especially for big graphs of interest. More recently, the use of Graphics processing units (GPU) has been promising, but challenging because of limited global memory of GPU’s, and irregular structures of real-world graphs. In this paper, we present a GPU based linear-algebraic formulation and implementation of BFS, called TurboBFS, that exhibits excellent scalability on unweighted, undirected or directed sparse graphs of arbitrary structure. We demonstrate that our algorithms obtain up to 40 GTEPs, and are on average 15.7x, 5.8x, and 1.8x faster than the other state-of-the-art algorithms implemented on the SuiteSparse:GraphBLAS, GraphBLAST, and gunrock libraries respectively. The codes to implement the algorithms proposed in this paper are available at https://github.com/pcdslab.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129098991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00156
Bogdan Mucenic, Chaitanya Kaligotla, Abby Stevens, J. Ozik, Nicholson T. Collier, C. Macal
We present our development of load balancing algorithms to efficiently distribute and parallelize the running of large-scale complex agent-based modeling (ABM) simulators on High-Performance Computing (HPC) resources. Our algorithm is based on partitioning the co-location network that emerges from an ABM’s underlying synthetic population. Variations of this algorithm are experimentally applied to investigate algorithmic choices on two factors that affect run-time performance. We report these experiments’ results on the CityCOVID ABM, built to model the spread of COVID-19 in the Chicago metropolitan region.
{"title":"Load Balancing Schemes for Large Synthetic Population-Based Complex Simulators","authors":"Bogdan Mucenic, Chaitanya Kaligotla, Abby Stevens, J. Ozik, Nicholson T. Collier, C. Macal","doi":"10.1109/IPDPSW52791.2021.00156","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00156","url":null,"abstract":"We present our development of load balancing algorithms to efficiently distribute and parallelize the running of large-scale complex agent-based modeling (ABM) simulators on High-Performance Computing (HPC) resources. Our algorithm is based on partitioning the co-location network that emerges from an ABM’s underlying synthetic population. Variations of this algorithm are experimentally applied to investigate algorithmic choices on two factors that affect run-time performance. We report these experiments’ results on the CityCOVID ABM, built to model the spread of COVID-19 in the Chicago metropolitan region.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114117475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/IPDPSW52791.2021.00086
Peter Oostema, F. Franchetti
Spatial graph embedding is a technique for placing graphs in space used for visualization and graph analytics. The general goal is to place connected nodes close together while spreading apart all others. Previous work has looked at spatial graph embedding in 2 or 3 dimensions. These used high performance libraries and fast algorithms for N-body simulation. We expand into higher dimensions to find what it can be useful for. Using an arbitrary number of dimensions allows all unweighted graph to have exact edge lengths, as n nodes can all be one distance part in a n − 1 dimensional simplex. This increases the complexity of the simulation, so we provide an efficient GPU implementation in high dimensions. Although high dimensional embeddings cannot be easily visualized they find a consistent structure which can be used for graph analytics. Problems this has been used to solve are graph isomorphism and graph coloring.
{"title":"Leveraging High Dimensional Spatial Graph Embedding as a Heuristic for Graph Algorithms","authors":"Peter Oostema, F. Franchetti","doi":"10.1109/IPDPSW52791.2021.00086","DOIUrl":"https://doi.org/10.1109/IPDPSW52791.2021.00086","url":null,"abstract":"Spatial graph embedding is a technique for placing graphs in space used for visualization and graph analytics. The general goal is to place connected nodes close together while spreading apart all others. Previous work has looked at spatial graph embedding in 2 or 3 dimensions. These used high performance libraries and fast algorithms for N-body simulation. We expand into higher dimensions to find what it can be useful for. Using an arbitrary number of dimensions allows all unweighted graph to have exact edge lengths, as n nodes can all be one distance part in a n − 1 dimensional simplex. This increases the complexity of the simulation, so we provide an efficient GPU implementation in high dimensions. Although high dimensional embeddings cannot be easily visualized they find a consistent structure which can be used for graph analytics. Problems this has been used to solve are graph isomorphism and graph coloring.","PeriodicalId":170832,"journal":{"name":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128158098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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