A complete system design methodology for next-generation wireless systems must encompass 3 radically different design domains: (1) mixed-signal and analog, (2) baseband communications and signal processing, and (3) embedded protocol controllers. Further, this design methodology must facilitate the flow from a high-level specification into an implementation. A skeleton design flow that makes use of existing point tools is presented, and areas for improvement are highlighted.
{"title":"A design methodology for highly-integrated wireless communications systems","authors":"T. Truman, R. Brodersen","doi":"10.1109/IWV.1998.667118","DOIUrl":"https://doi.org/10.1109/IWV.1998.667118","url":null,"abstract":"A complete system design methodology for next-generation wireless systems must encompass 3 radically different design domains: (1) mixed-signal and analog, (2) baseband communications and signal processing, and (3) embedded protocol controllers. Further, this design methodology must facilitate the flow from a high-level specification into an implementation. A skeleton design flow that makes use of existing point tools is presented, and areas for improvement are highlighted.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125079839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we discuss the design of a multi-port SRAM which is an essential component in a shared memory system. Proposed is an area efficient memory cell structure which is better in cell stability and more immune to cross-talk noise. Some special circuit techniques are employed in order to accommodate the high capacity (32 Kbs) and the high number of ports (5R and 2W) required by the application. The 7-port memory is implemented in a 0.25 /spl mu/m CMOS technology. Analyses prove that 200 MHz high speed operation, low peak power and complex read-write access functionality are achieved. The authors also show that such a design can be easily extended and adapted to other shared memory systems.
{"title":"A 32 Kbs on-chip memory with high port-multiplicity (5 reads and 2 writes) for effective implementation of shared memory systems","authors":"T. Tsang, Ching Li, M. Kalluri","doi":"10.1109/IWV.1998.667139","DOIUrl":"https://doi.org/10.1109/IWV.1998.667139","url":null,"abstract":"In this paper, we discuss the design of a multi-port SRAM which is an essential component in a shared memory system. Proposed is an area efficient memory cell structure which is better in cell stability and more immune to cross-talk noise. Some special circuit techniques are employed in order to accommodate the high capacity (32 Kbs) and the high number of ports (5R and 2W) required by the application. The 7-port memory is implemented in a 0.25 /spl mu/m CMOS technology. Analyses prove that 200 MHz high speed operation, low peak power and complex read-write access functionality are achieved. The authors also show that such a design can be easily extended and adapted to other shared memory systems.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127697957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. van Meerbergen, A. Timmer, J. Leijten, F. Harmsze, M. Strik
The continuing trend towards higher integration densities of ICs makes systems-on-a-chip possible. For well defined application domains "silicon platforms" must be defined which combine efficient implementations with programmability. Platforms are heterogeneous reconfigurable multiprocessor architectures supporting a variety of communication and computation models. As a consequence designers are facing a large architecture space with new possibilities for new architectures. To exploit these opportunities a better understanding of system level architectures is necessary. A first step in this direction is to learn from design exercises. Eventually this may lead towards a system level design method.
{"title":"Experiences with system level design for consumer ICs","authors":"J. van Meerbergen, A. Timmer, J. Leijten, F. Harmsze, M. Strik","doi":"10.1109/IWV.1998.667108","DOIUrl":"https://doi.org/10.1109/IWV.1998.667108","url":null,"abstract":"The continuing trend towards higher integration densities of ICs makes systems-on-a-chip possible. For well defined application domains \"silicon platforms\" must be defined which combine efficient implementations with programmability. Platforms are heterogeneous reconfigurable multiprocessor architectures supporting a variety of communication and computation models. As a consequence designers are facing a large architecture space with new possibilities for new architectures. To exploit these opportunities a better understanding of system level architectures is necessary. A first step in this direction is to learn from design exercises. Eventually this may lead towards a system level design method.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130218898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power consumption is an increasingly important consideration in the design of mixed hardware/software systems. This work defines the notion of instruction subsetting and explores its use as a means of reducing power consumption from the system level of design. Instruction subsetting is defined as creating an application specific instruction set processor from a more general processor such as a DSP. Although not as effective as an ASIC solution, instruction subsetting provides much of the power savings while maintaining some level of programmability. Instruction set choice strongly affects the savings. We synthesized 5 ASIPs through place and route and found that a poorly chosen instruction set may consume more than 4 times the energy of an ASIP with a proper instruction set choice. This finding will allow designers to consider another set of trade-offs in their hardware/software design space exploration.
{"title":"Instruction subsetting: Trading power for programmability","authors":"W. Dougherty, D. Pursley, D. E. Thomas","doi":"10.1109/IWV.1998.667112","DOIUrl":"https://doi.org/10.1109/IWV.1998.667112","url":null,"abstract":"Power consumption is an increasingly important consideration in the design of mixed hardware/software systems. This work defines the notion of instruction subsetting and explores its use as a means of reducing power consumption from the system level of design. Instruction subsetting is defined as creating an application specific instruction set processor from a more general processor such as a DSP. Although not as effective as an ASIC solution, instruction subsetting provides much of the power savings while maintaining some level of programmability. Instruction set choice strongly affects the savings. We synthesized 5 ASIPs through place and route and found that a poorly chosen instruction set may consume more than 4 times the energy of an ASIP with a proper instruction set choice. This finding will allow designers to consider another set of trade-offs in their hardware/software design space exploration.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116232260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Power Electronic Building Block (PEBB) concept is to develop a general purpose power controller capable of performing numerous electrical conversion functions simply through software reconfiguration. It is also intended to facilitate greater modularity in power electronic systems. However, realization of PEBB systems is a non-trivial endeavor because of electromagnetic interference, thermal management, packaging, and technological barriers. In this paper, we present these barriers along with some solutions.
{"title":"Design issues in power electronic building block (PEBB) system integration","authors":"K. Kornegay","doi":"10.1109/IWV.1998.667114","DOIUrl":"https://doi.org/10.1109/IWV.1998.667114","url":null,"abstract":"The Power Electronic Building Block (PEBB) concept is to develop a general purpose power controller capable of performing numerous electrical conversion functions simply through software reconfiguration. It is also intended to facilitate greater modularity in power electronic systems. However, realization of PEBB systems is a non-trivial endeavor because of electromagnetic interference, thermal management, packaging, and technological barriers. In this paper, we present these barriers along with some solutions.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114764357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-level specifications of the behavior of information processing systems consist of data and control flow descriptions as well as of timing requirements to be met by a feasible implementation. These requirements are in general captured as bounds on the processing times of periodic and aperiodic computational tasks. Cyclic process nets are introduced as a high-level computational model for representing both flow information and timing bounds of information processing systems. Different iteration and varying computation times which are characteristic for HW/SW implementations in embedded systems, combined with the associated functional description yield then a high-level behavioral specification of such systems. As a main result, the presented scheduling algorithm detects hidden time intervals in the specification which may then be exploited as a resource for HW/SW partitioning purposes during design space exploration. Thus, the proposed cyclic process nets form a foundation for codesign tasks in embedded systems synthesis. Finally, the resulting design flow is discussed by means of an application example.
{"title":"Cyclic process nets as a high-level behavioral specification model for embedded systems synthesis","authors":"W. Boßung, Sorin A. Huss","doi":"10.1109/IWV.1998.667134","DOIUrl":"https://doi.org/10.1109/IWV.1998.667134","url":null,"abstract":"High-level specifications of the behavior of information processing systems consist of data and control flow descriptions as well as of timing requirements to be met by a feasible implementation. These requirements are in general captured as bounds on the processing times of periodic and aperiodic computational tasks. Cyclic process nets are introduced as a high-level computational model for representing both flow information and timing bounds of information processing systems. Different iteration and varying computation times which are characteristic for HW/SW implementations in embedded systems, combined with the associated functional description yield then a high-level behavioral specification of such systems. As a main result, the presented scheduling algorithm detects hidden time intervals in the specification which may then be exploited as a resource for HW/SW partitioning purposes during design space exploration. Thus, the proposed cyclic process nets form a foundation for codesign tasks in embedded systems synthesis. Finally, the resulting design flow is discussed by means of an application example.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123493652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Chandrakasan, J. Goodman, J. Kao, W. Rabiner, T. Simon
This paper describes the system design of a low-power wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties such as the network configuration and data statistics are exploited to minimize computational switching. Embedded power supplies systems are also used to minimize energy dissipation under varying temperature, process parameters and computational workload. Since sensor systems often operate in burst mode with long idle periods, emphasis must be placed on reducing system leakage power through the use of emerging technologies and circuit techniques.
{"title":"Design of a low-power wireless camera","authors":"A. Chandrakasan, J. Goodman, J. Kao, W. Rabiner, T. Simon","doi":"10.1109/IWV.1998.667109","DOIUrl":"https://doi.org/10.1109/IWV.1998.667109","url":null,"abstract":"This paper describes the system design of a low-power wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties such as the network configuration and data statistics are exploited to minimize computational switching. Embedded power supplies systems are also used to minimize energy dissipation under varying temperature, process parameters and computational workload. Since sensor systems often operate in burst mode with long idle periods, emphasis must be placed on reducing system leakage power through the use of emerging technologies and circuit techniques.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123865052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper examines the desirability and viability of state-of-the-art system design at the university. To put the problem in perspective, a number of actual designs exercises, executed at UC Berkeley over the last decade, will be examined. A number of potential models for success are proposed and analyzed. While this paper might provide some insight, it is surely hoped that it might serve as the basis for an ongoing discussion that might lead to an (inter)national infrastructure for system-design in the long term.
{"title":"Experiences and challenges in system design","authors":"J. Rabaey","doi":"10.1109/IWV.1998.667105","DOIUrl":"https://doi.org/10.1109/IWV.1998.667105","url":null,"abstract":"This paper examines the desirability and viability of state-of-the-art system design at the university. To put the problem in perspective, a number of actual designs exercises, executed at UC Berkeley over the last decade, will be examined. A number of potential models for success are proposed and analyzed. While this paper might provide some insight, it is surely hoped that it might serve as the basis for an ongoing discussion that might lead to an (inter)national infrastructure for system-design in the long term.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"21 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114102278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The implementation of entire systems on VLSI chips provides an opportunity for a top-down test strategy. This is possible if the systems designer is familiar with the basic concepts in test, design for testability, and system diagnosis. The paper proposes a two-step education program. The first coarse, "Essentials of Electronic Testing ", teaches the basic principles of testing. It is an undergraduate-level course and should be included in the core curriculum in addition to a VLSI design course. The second course, "Advanced Concepts in VLSI Testing", is a graduate-level course. It is useful for VLSI CAD engineers and for researchers.
{"title":"Test education for VLSI systems design engineers","authors":"V. Agrawal","doi":"10.1109/IWV.1998.667117","DOIUrl":"https://doi.org/10.1109/IWV.1998.667117","url":null,"abstract":"The implementation of entire systems on VLSI chips provides an opportunity for a top-down test strategy. This is possible if the systems designer is familiar with the basic concepts in test, design for testability, and system diagnosis. The paper proposes a two-step education program. The first coarse, \"Essentials of Electronic Testing \", teaches the basic principles of testing. It is an undergraduate-level course and should be included in the core curriculum in addition to a VLSI design course. The second course, \"Advanced Concepts in VLSI Testing\", is a graduate-level course. It is useful for VLSI CAD engineers and for researchers.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124004591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Operation of wireless communication systems with mixed signal circuits operating in gigahertz range frequencies has raised the need for new test and design methodologies to meet the current and future market requirements. This paper discusses the challenges arising in mixed signal portable wireless packaging with emphasis on design and test. Solutions being pursued at PRC are also discussed.
{"title":"Mixed signal portable wireless packaging design and test challenges","authors":"M. Swaminathan, S. Pannala","doi":"10.1109/IWV.1998.667124","DOIUrl":"https://doi.org/10.1109/IWV.1998.667124","url":null,"abstract":"Operation of wireless communication systems with mixed signal circuits operating in gigahertz range frequencies has raised the need for new test and design methodologies to meet the current and future market requirements. This paper discusses the challenges arising in mixed signal portable wireless packaging with emphasis on design and test. Solutions being pursued at PRC are also discussed.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130805595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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