Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972803
K. Hamaguchi
This paper handles symbolic simulation for high-level design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named "symbolic function table" and "synchronization". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our prototype symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics, up to tens of thousands of cycles.
{"title":"Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions","authors":"K. Hamaguchi","doi":"10.1109/HLDVT.2001.972803","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972803","url":null,"abstract":"This paper handles symbolic simulation for high-level design descriptions including uninterpreted functions. Two new heuristics are introduced, which are named \"symbolic function table\" and \"synchronization\". In the experiment, the equivalence of a hardware/software codesign was checked up to a given finite number of cycles, which is composed of a behavioral design, that is, a small DSP program written in C, and its register-transfer-level implementation, a VLIW architecture with an assembly program. Our prototype symbolic simulator succeeded in checking the equivalence of the two descriptions which were not tractable without the heuristics, up to tens of thousands of cycles.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133508456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972807
S. Shukla, Rajesh K. Gupta
System Level Power Management policies are typically based on moving the system to various power management states, in order to achieve minimum wastage of power The major challenge in devising such strategies is that the input task arrival rates to a system is usually unpredictable, and hence the power management strategies have to be designed as on-line algorithms. These algorithms are aimed at optimizing wasted power in the face of nondeterministic task arrivals. Previous works on evaluating power management strategies for optimality, have used trace driven simulations, and competitive analysis. In this work we build upon the competitive analysis based paradigm. Our work views a power management strategy as a winning strategy in a two player game, between the power management algorithm, and a non-deterministic adversary. With the power of non-determinism, we can generate the worst possible scenarios in terms of possible traces of tasks. Such scenarios not only disprove conjectured bounds on the optimality of a power management strategy, but also guides the designer towards a better policy. One could also prove such bounds automatically. To achieve these, we exploit model checkers used in formal verification. However, specific tools which are focused mainly on this kind of power management strategies are under development, which would alleviate some of the state explosion problems inherent in model checking techniques.
{"title":"A model checking approach to evaluating system level dynamic power management policies for embedded systems","authors":"S. Shukla, Rajesh K. Gupta","doi":"10.1109/HLDVT.2001.972807","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972807","url":null,"abstract":"System Level Power Management policies are typically based on moving the system to various power management states, in order to achieve minimum wastage of power The major challenge in devising such strategies is that the input task arrival rates to a system is usually unpredictable, and hence the power management strategies have to be designed as on-line algorithms. These algorithms are aimed at optimizing wasted power in the face of nondeterministic task arrivals. Previous works on evaluating power management strategies for optimality, have used trace driven simulations, and competitive analysis. In this work we build upon the competitive analysis based paradigm. Our work views a power management strategy as a winning strategy in a two player game, between the power management algorithm, and a non-deterministic adversary. With the power of non-determinism, we can generate the worst possible scenarios in terms of possible traces of tasks. Such scenarios not only disprove conjectured bounds on the optimality of a power management strategy, but also guides the designer towards a better policy. One could also prove such bounds automatically. To achieve these, we exploit model checkers used in formal verification. However, specific tools which are focused mainly on this kind of power management strategies are under development, which would alleviate some of the state explosion problems inherent in model checking techniques.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128195227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972817
R. Kaivola, N. Narasimhan
We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium(R)4 microprocessor. The verification is based on a combination of theorem-proving and model-checking tasks performed in the Forte hardware verification environment. The tasks are tightly integrated to accomplish complete verification of the multiplier hardware coupled with the rounder logic. The approach does not rely on specialized representations like binary moment diagrams or its variants.
{"title":"Formal verification of the Pentium(R) 4 multiplier","authors":"R. Kaivola, N. Narasimhan","doi":"10.1109/HLDVT.2001.972817","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972817","url":null,"abstract":"We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium(R)4 microprocessor. The verification is based on a combination of theorem-proving and model-checking tasks performed in the Forte hardware verification environment. The tasks are tightly integrated to accomplish complete verification of the multiplier hardware coupled with the rounder logic. The approach does not rely on specialized representations like binary moment diagrams or its variants.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124338605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972812
Srikanth Arekapudi, Fei Xin, Jinzheng Peng, I. Harris
We present an ATPG algorithm for the covalidation of hardware-software systems. Specifically, we target the detection of timing-induced functional errors in the design by using a design fault model which we propose. The computational time required by the test generation process is sufficiently low that the ATPG tool can be used by a designer to achieve a significant reduction in validation cost.
{"title":"Test pattern generation for timing-induced functional errors in hardware-software systems","authors":"Srikanth Arekapudi, Fei Xin, Jinzheng Peng, I. Harris","doi":"10.1109/HLDVT.2001.972812","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972812","url":null,"abstract":"We present an ATPG algorithm for the covalidation of hardware-software systems. Specifically, we target the detection of timing-induced functional errors in the design by using a design fault model which we propose. The computational time required by the test generation process is sufficiently low that the ATPG tool can be used by a designer to achieve a significant reduction in validation cost.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"90 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129214178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972826
G. Parthasarathy, Chung-Yang Huang, K. Cheng
We analyze the performance of satisfiability (SAT) and Automatic Test Pattern Generation (ATPG) algorithms in two state-of-the-art solvers. The goal is to best understand how features of each solver are suited for hardware verification. For ATPG, we analyze depth-first and breadth-first decision orderings and effects of two weighting heuristics in the decision ordering, and also study the effect of randomization of decisions. Features of ATPG and SAT that affect their robustness and flexibility on real circuits are studied, and the two solvers are compared on 24 industrial circuits. We further analyze the results to identify the strengths and shortcomings of each solver. This will enable incorporation of features from each solver in order to optimize performance, since they both operate on the same principles.
{"title":"An analysis of ATPG and SAT algorithms for formal verification","authors":"G. Parthasarathy, Chung-Yang Huang, K. Cheng","doi":"10.1109/HLDVT.2001.972826","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972826","url":null,"abstract":"We analyze the performance of satisfiability (SAT) and Automatic Test Pattern Generation (ATPG) algorithms in two state-of-the-art solvers. The goal is to best understand how features of each solver are suited for hardware verification. For ATPG, we analyze depth-first and breadth-first decision orderings and effects of two weighting heuristics in the decision ordering, and also study the effect of randomization of decisions. Features of ATPG and SAT that affect their robustness and flexibility on real circuits are studied, and the two solvers are compared on 24 industrial circuits. We further analyze the results to identify the strengths and shortcomings of each solver. This will enable incorporation of features from each solver in order to optimize performance, since they both operate on the same principles.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126434944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972810
M. Ciesielski, P. Kalla, Zhihong Zeng, B. Rouzeyre
A new, compact, canonical representation for arithmetic expressions, called Taylor expansion diagram, is presented. This representation is based on a non-binary decomposition principle. It treats the expression as a continuous, differentiable function and applies Taylor series expansion recursively over its symbolic variables. The resulting Taylor expansion diagram (TED) is canonical for a fixed variable order. We present a theory of TED, and show how to obtain a reduced, normalized representation. We demonstrate that it has linear space complexity for arbitrarily complex polynomials, while time complexity to generate the representation is comparable to that of *BMD. The proposed TED representation is intended to facilitate the verification of RTL specifications and hard. ware implementations of arithmetic designs, and especially the equivalence checking of complex arithmetic expressions that arise in symbolic verification.
{"title":"Taylor expansion diagrams: a new representation for RTL verification","authors":"M. Ciesielski, P. Kalla, Zhihong Zeng, B. Rouzeyre","doi":"10.1109/HLDVT.2001.972810","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972810","url":null,"abstract":"A new, compact, canonical representation for arithmetic expressions, called Taylor expansion diagram, is presented. This representation is based on a non-binary decomposition principle. It treats the expression as a continuous, differentiable function and applies Taylor series expansion recursively over its symbolic variables. The resulting Taylor expansion diagram (TED) is canonical for a fixed variable order. We present a theory of TED, and show how to obtain a reduced, normalized representation. We demonstrate that it has linear space complexity for arbitrarily complex polynomials, while time complexity to generate the representation is comparable to that of *BMD. The proposed TED representation is intended to facilitate the verification of RTL specifications and hard. ware implementations of arithmetic designs, and especially the equivalence checking of complex arithmetic expressions that arise in symbolic verification.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133929832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972801
Nabarun Bhattacharyya, A. Wang
Configurable processor cows me replacing standard CPU cores for meeting the complexities of System on a Chip designs, since standard cores often prove inadequate in performance without special hardware. Xtensa, a fully configurable and extensible processor core, allows users to add new instructions to the processor core optimized for their application. This kind of flexible architecture demands innovative verification techniques, since the instruction set of the processor as well as the pipeline model is no longer fixed. Here we describe a methodology for verifying the implementation of such processors and extensions based on an Instruction Set Architecture description. This method automatically generates micro-architectural tests without specific knowledge of the implementation. This is extremely powerful in the verification of configurable processors with extensible instruction sets and pipeline models.
{"title":"Automatic test generation for micro-architectural verification of configurable microprocessor cores with user extensions","authors":"Nabarun Bhattacharyya, A. Wang","doi":"10.1109/HLDVT.2001.972801","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972801","url":null,"abstract":"Configurable processor cows me replacing standard CPU cores for meeting the complexities of System on a Chip designs, since standard cores often prove inadequate in performance without special hardware. Xtensa, a fully configurable and extensible processor core, allows users to add new instructions to the processor core optimized for their application. This kind of flexible architecture demands innovative verification techniques, since the instruction set of the processor as well as the pipeline model is no longer fixed. Here we describe a methodology for verifying the implementation of such processors and extensions based on an Instruction Set Architecture description. This method automatically generates micro-architectural tests without specific knowledge of the implementation. This is extremely powerful in the verification of configurable processors with extensible instruction sets and pipeline models.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-07DOI: 10.1109/HLDVT.2001.972813
M. Jersak, K. Richter, R. Ernst
Sophisticated models of event streams including jitter and bursts as well as the possibility to specify a variety of system-level timing constraints are prerequisites for modem analysis and synthesis techniques in the area of embedded real-time systems. Currently, there is no commonly used specification that models events and timing constraints in a sufficiently general way. In this paper, we first identify a duality between event models and timing constraints and as a result present a specification that can be used for both. Our specification covers most current analysis and synthesis techniques and is easily extensible. We then show how the duality between event models and timing constraints can be applied at different points in a design flow. A real-time video transmission is used as an example.
{"title":"Combining complex event models and timing constraints","authors":"M. Jersak, K. Richter, R. Ernst","doi":"10.1109/HLDVT.2001.972813","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972813","url":null,"abstract":"Sophisticated models of event streams including jitter and bursts as well as the possibility to specify a variety of system-level timing constraints are prerequisites for modem analysis and synthesis techniques in the area of embedded real-time systems. Currently, there is no commonly used specification that models events and timing constraints in a sufficiently general way. In this paper, we first identify a duality between event models and timing constraints and as a result present a specification that can be used for both. Our specification covers most current analysis and synthesis techniques and is easily extensible. We then show how the duality between event models and timing constraints can be applied at different points in a design flow. A real-time video transmission is used as an example.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126409616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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