Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.8986166
K. Seidel, K. Biedermann, J. V. Houdt, T. Ali, R. Hoffmann, K. Kühnel, M. Czernohorsky, M. Rudolph, B. Pätzold, P. Steinke, K. Zimmermann
The utilization of FeFET technology in NAND based architectures is dependent on the role of pass voltage disturb of pass cells during the readout of selected cells. This disturb effect becomes dependent on the FeFET stack parameters and potential optimization for a disturb free operation. In this paper, the impact of pass voltage on the disturb properties of a standard 10 nm Si-doped hafnium oxide (HSO) based FeFETs in a twin gate NAND string is reported. This shows a rather low margin between the pass voltage and strong disturb of pass cells and suggests FeFET stack optimization. A laminate HSO based FE stack (2 × 10nm) with an optimized interface layer (IL) is proposed in benchmark to the standard one to achieve a higher pass window for disturb free operation of the NAND cells. $text{A}sim 2text{x}$ pass window is obtained on the laminated FeFET stack compared to the standard one without jeopardizing the optimal write conditions of the FeFET. The pass voltage disturb properties of unselected NAND cells is reported with emphasis on the potential of an optimized laminate based stack to reduce the pass disturb effect.
{"title":"Gate Stack Optimization Toward Disturb-Free Operation of Ferroelectric HSO based FeFET for NAND Applications","authors":"K. Seidel, K. Biedermann, J. V. Houdt, T. Ali, R. Hoffmann, K. Kühnel, M. Czernohorsky, M. Rudolph, B. Pätzold, P. Steinke, K. Zimmermann","doi":"10.1109/NVMTS47818.2019.8986166","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.8986166","url":null,"abstract":"The utilization of FeFET technology in NAND based architectures is dependent on the role of pass voltage disturb of pass cells during the readout of selected cells. This disturb effect becomes dependent on the FeFET stack parameters and potential optimization for a disturb free operation. In this paper, the impact of pass voltage on the disturb properties of a standard 10 nm Si-doped hafnium oxide (HSO) based FeFETs in a twin gate NAND string is reported. This shows a rather low margin between the pass voltage and strong disturb of pass cells and suggests FeFET stack optimization. A laminate HSO based FE stack (2 × 10nm) with an optimized interface layer (IL) is proposed in benchmark to the standard one to achieve a higher pass window for disturb free operation of the NAND cells. $text{A}sim 2text{x}$ pass window is obtained on the laminated FeFET stack compared to the standard one without jeopardizing the optimal write conditions of the FeFET. The pass voltage disturb properties of unselected NAND cells is reported with emphasis on the potential of an optimized laminate based stack to reduce the pass disturb effect.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/NVMTS47818.2019.9043369
J. Postel-Pellerin, Hussein Bazzi, H. Aziza, P. Canet, M. Moreau, V. D. Marca, A. Harb
A novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, the voltage applied to the cells of the memory array is fixed at the median SET voltage of the distribution, to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed eleven NIST tests out of fifteen without any post-processing.
{"title":"True random number generation exploiting SET voltage variability in resistive RAM memory arrays","authors":"J. Postel-Pellerin, Hussein Bazzi, H. Aziza, P. Canet, M. Moreau, V. D. Marca, A. Harb","doi":"10.1109/NVMTS47818.2019.9043369","DOIUrl":"https://doi.org/10.1109/NVMTS47818.2019.9043369","url":null,"abstract":"A novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, the voltage applied to the cells of the memory array is fixed at the median SET voltage of the distribution, to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed eleven NIST tests out of fifteen without any post-processing.","PeriodicalId":199112,"journal":{"name":"2019 19th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127868894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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