Pub Date : 2023-06-20DOI: 10.1109/ISVLSI59464.2023.10238676
Ivan Saraiva Silva, Francisco Carlos Silva Junior
To improve reconfigurable architectures' programmability, a CGRA named X4CP32 was proposed in early 2003. With two execution modes (programming execution mode and reconfigurable execution mode), X4CP32 offered an architectural model providing support to use the array through programming or configuration. In other words, a statical or dynamical procedure defines the processing elements' operations. This paper revisits this CGRA design using modern techniques and tools, notably the GEM5 simulator, the McPAT framework, and CACTI. Also, a hardware unit providing transparent and dynamic reconfiguration was incorporated. Furthermore, the design replaced an unknown and naive embedded microprocessor using RISC-V. Using a modern embedded processor, transparent and dynamic reconfiguration, and a thin array allows the design of a reconfigurable multicore able to execute up to 88% faster and with 55% less energy than a regular multicore. (Abstract)
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Pub Date : 2023-06-20DOI: 10.1109/ISVLSI59464.2023.10238503
Yi Xiao, Yixin Xu, Shan Deng, Zijian Zhao, Sumitha George, Kai Ni, N. Vijaykrishnan
With the proliferation of data-intensive applications, various logic-in-memory (LIM)/ in-memory computing (IMC) solutions are emerging. These solutions aim to mitigate the von Neumann bottleneck caused by frequent data transfer between computational units and memory arrays. Ferroelectric devices such as ferroelectric random access memory (FeRAM), ferroelectric FET (FeFET) and ferroelectric tunnel junction (FTJ) etc., are promising nonvolatile memory (NVM) candidates for the LIM application due to their lower write power compared to competing NVM technologies. In this work, we propose a compact ferroelectric 2T-(n+1) C LIM cell to implement ANDOR logic based on the concept of quasi-nondestructive readout (QNRO) FeRAM. In comparison with 1T-1C FeRAM and 1T FeFET, our structure has both distinguished write and read characteristics. The n-bit AND-OR logic accomplished by our design has $2mathrm{n}times$ performance improvement and $5.1times$ integration density gain against the conventional CMOS logic. Additionally, the area efficiency of our design can be further enhanced by 3D integration. We then verify the correctness of a 3-bit AND-OR logic gate by conducting circuit simulation and device experiments. The simulation results demonstrate a $sim 70$ ON/OFF ratio with the ON/OFF current window of $gt866mathrm{nA}$, and for the experimental results the $mathrm{ON}/mathrm{OFF}$ ratio is 3.8 with the current window of $gt68mumathrm{A}$.
随着数据密集型应用程序的激增，各种内存中逻辑(LIM)/内存中计算(IMC)解决方案正在出现。这些解决方案旨在缓解由计算单元和存储阵列之间频繁数据传输引起的冯诺依曼瓶颈。铁电器件，如铁电随机存取存储器(FeRAM)、铁电场效应晶体管(FeFET)和铁电隧道结(FTJ)等，由于与竞争的非易失性存储器技术相比，它们的写入功率更低，因此是非易失性存储器(NVM)在LIM应用中很有前途。在这项工作中，我们提出了一个紧凑的铁电2T-(n+1) C LIM单元来实现基于准无损读出(QNRO) FeRAM概念的ANDOR逻辑。与1T- 1c FeRAM和1T ffet相比，我们的结构具有不同的写入和读取特性。与传统CMOS逻辑相比，本设计实现的n位与或逻辑具有$2mathrm{n}times$性能改进和$5.1times$集成密度增益。此外，我们设计的面积效率可以通过3D集成进一步提高。然后，我们通过电路仿真和器件实验验证了3位与或逻辑门的正确性。仿真结果表明，在开/关电流窗为$gt866mathrm{nA}$时，开关比为$sim 70$;实验结果表明，在电流窗为$gt68mumathrm{A}$时，开关比为$mathrm{ON}/mathrm{OFF}$ 3.8。
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Pub Date : 2021-06-09DOI: 10.1109/ISVLSI59464.2023.10238656
Yerzhan Mustafa, Selçuk Köse
Switched-capacitor (SC) DC-DC voltage converters are widely used in power delivery and management of modern integrated circuits. Connected to a common supply voltage, SC converters exhibit cross-regulation/coupling effects among loads connected to different SC converter stages due to the shared components such as switches, capacitors, and parasitic elements. The coupling effects between SC converter stages can potentially be used in covert communication, where two or more entities (e.g., loads) illegitimately establish a communication channel to exchange malicious information stealthily. To qualitatively analyze the coupling effects, a novel modeling technique is proposed based on the multi-port network theory. The fast and slow switching limit (FSL and SSL) equivalent resistance concepts are used to analytically determine the impact of each design parameter such as switch resistance, flying capacitance, switching frequency, and parasitic resistance. A three-stage 2:1 SC converter supplying three different loads is considered as a case study to verify the proposed modeling technique.
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