Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629331
Raghavan Kumar, W. Burleson
Physically Unclonable Functions (PUFs) are lightweight cryptographic primitives for generating unique signatures from complex manufacturing variations. In this work, we present a current-based PUF designed using a generalized lithographic simulation framework for improving inter-die and inter-wafer uniqueness. The sensitivity of the circuit to manufacturing variations is enhanced by placing the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. Simulation results show that the litho-aware current based PUF has improved inter- and intra-distance over the conventional current-based PUF. The litho-aware PUF consumes about 0.034 pico joules of energy per response bit, which is substantially better than delay-based PUF implementations.
{"title":"Litho-aware and low power design of a secure current-based physically unclonable function","authors":"Raghavan Kumar, W. Burleson","doi":"10.1109/ISLPED.2013.6629331","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629331","url":null,"abstract":"Physically Unclonable Functions (PUFs) are lightweight cryptographic primitives for generating unique signatures from complex manufacturing variations. In this work, we present a current-based PUF designed using a generalized lithographic simulation framework for improving inter-die and inter-wafer uniqueness. The sensitivity of the circuit to manufacturing variations is enhanced by placing the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. Simulation results show that the litho-aware current based PUF has improved inter- and intra-distance over the conventional current-based PUF. The litho-aware PUF consumes about 0.034 pico joules of energy per response bit, which is substantially better than delay-based PUF implementations.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78483410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629257
Cheng-Wen Wu
In the past few years, we have witnessed the energy crisis and the financial tsunami that played an unwanted duo, changing the world in many aspects that affect most of us. While companies are working hard in getting out of the slump, many research organizations are rethinking how their R&D budget should be invested. We consider advanced research activities stressing ultra-low power and energy-efficient circuits and systems a top-priority direction. Among our list of R&D topics are ultra-low voltage circuits and systems, energy-harvesting circuits and systems, 3D integration based on the Through-Silicon-Via (TSV) technology, and normally-off computing technologies. To be successful in integrating the basic technologies developed, a holistic approach should be considered. Therefore, in addition to introduction and discussion of the above research topics at ITRI, I will also discuss a system-level modeling and evaluation platform, emphasizing power/energy efficiency.
{"title":"Holistic approach to low-power system design","authors":"Cheng-Wen Wu","doi":"10.1109/ISLPED.2013.6629257","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629257","url":null,"abstract":"In the past few years, we have witnessed the energy crisis and the financial tsunami that played an unwanted duo, changing the world in many aspects that affect most of us. While companies are working hard in getting out of the slump, many research organizations are rethinking how their R&D budget should be invested. We consider advanced research activities stressing ultra-low power and energy-efficient circuits and systems a top-priority direction. Among our list of R&D topics are ultra-low voltage circuits and systems, energy-harvesting circuits and systems, 3D integration based on the Through-Silicon-Via (TSV) technology, and normally-off computing technologies. To be successful in integrating the basic technologies developed, a holistic approach should be considered. Therefore, in addition to introduction and discussion of the above research topics at ITRI, I will also discuss a system-level modeling and evaluation platform, emphasizing power/energy efficiency.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72974724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629307
Yu Chen, Mingoo Seok, S. Nowick
Asynchronous dynamic pipelines are increasingly being used, including in recent commercial design flows, since they simultaneously provide high-performance, clock-free operation and delay-insensitive communication. While they also show promise for energy-efficient ultra-low-voltage circuits, with always-on keepers, these circuits exhibit severe robustness issues. In this paper, an adaptive keeper solution is introduced, to eliminate write contention issues. Arbitrary unknown data rates and congestion must be safely handled, without a reference clock, hence conventional solutions for synchronous design cannot be applied. The proposed method, demonstrated in two widely-used pipelines (PS0, PCHB), directly addresses the asynchronous contention issue by dynamic monitoring of neighboring traffic at each pipeline stage. Simulations of a pipelined ripple-carry adder show correct operation at 0.3 V with energy improvements of up to 4.4× compared to a non-adaptive design. In addition, the approach also improves pipeline throughput by 24.4% and 17.4% at 0.6 V and nominal 1.0 V, respectively.
{"title":"Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control","authors":"Yu Chen, Mingoo Seok, S. Nowick","doi":"10.1109/ISLPED.2013.6629307","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629307","url":null,"abstract":"Asynchronous dynamic pipelines are increasingly being used, including in recent commercial design flows, since they simultaneously provide high-performance, clock-free operation and delay-insensitive communication. While they also show promise for energy-efficient ultra-low-voltage circuits, with always-on keepers, these circuits exhibit severe robustness issues. In this paper, an adaptive keeper solution is introduced, to eliminate write contention issues. Arbitrary unknown data rates and congestion must be safely handled, without a reference clock, hence conventional solutions for synchronous design cannot be applied. The proposed method, demonstrated in two widely-used pipelines (PS0, PCHB), directly addresses the asynchronous contention issue by dynamic monitoring of neighboring traffic at each pipeline stage. Simulations of a pipelined ripple-carry adder show correct operation at 0.3 V with energy improvements of up to 4.4× compared to a non-adaptive design. In addition, the approach also improves pipeline throughput by 24.4% and 17.4% at 0.6 V and nominal 1.0 V, respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80181890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629279
Mark Buckler, W. Burleson, G. Sadowski
After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given system's power budget. This brief paper and accompanying presentation discuss what options are available to designers who need to reduce NoC power consumption, their benefits, and their limitations. Techniques discussed here include general NoC system design as well as disruptive interconnect mediums and their associated strategies.
{"title":"Low-power Networks-on-Chip: Progress and remaining challenges","authors":"Mark Buckler, W. Burleson, G. Sadowski","doi":"10.1109/ISLPED.2013.6629279","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629279","url":null,"abstract":"After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given system's power budget. This brief paper and accompanying presentation discuss what options are available to designers who need to reduce NoC power consumption, their benefits, and their limitations. Techniques discussed here include general NoC system design as well as disruptive interconnect mediums and their associated strategies.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83617095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629330
Emily Bragg, Marisabel Guevara, Benjamin C. Lee
Today's largest datacenters dissipate megawatts of power. Efficiency is rapidly becoming the primary determinant of datacenter capability. To understand microarchitectural factors that affect efficiency, we must study datacenter workloads.
{"title":"Understanding query complexity and its implications for energy-efficient web search","authors":"Emily Bragg, Marisabel Guevara, Benjamin C. Lee","doi":"10.1109/ISLPED.2013.6629330","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629330","url":null,"abstract":"Today's largest datacenters dissipate megawatts of power. Efficiency is rapidly becoming the primary determinant of datacenter capability. To understand microarchitectural factors that affect efficiency, we must study datacenter workloads.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81019173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629262
Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar
We propose a framework that enables intensive computation on ultra-low power devices with discontinuous energy-harvesting supplies. We devise an optimization algorithm that efficiently partitions the applications into smaller computational steps during high-level synthesis. Our system finds low-overhead checkpoints that minimize recomputation cost due to power losses, then inserts the checkpoints at the design's registertransfer level. The checkpointing rate is automatically adapted to the source's realtime behavior. We evaluate our mechanisms on a battery-less RF energy-harvester platform. Extensive experiments targeting applications in medical implant devices demonstrate our approach's ability to successfully execute complex computations for various supply patterns with low time, energy, and area overheads.
{"title":"Automated checkpointing for enabling intensive applications on energy harvesting devices","authors":"Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar","doi":"10.1109/ISLPED.2013.6629262","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629262","url":null,"abstract":"We propose a framework that enables intensive computation on ultra-low power devices with discontinuous energy-harvesting supplies. We devise an optimization algorithm that efficiently partitions the applications into smaller computational steps during high-level synthesis. Our system finds low-overhead checkpoints that minimize recomputation cost due to power losses, then inserts the checkpoints at the design's registertransfer level. The checkpointing rate is automatically adapted to the source's realtime behavior. We evaluate our mechanisms on a battery-less RF energy-harvester platform. Extensive experiments targeting applications in medical implant devices demonstrate our approach's ability to successfully execute complex computations for various supply patterns with low time, energy, and area overheads.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86985132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629326
Zhongqi Li, Tao Li
Photonic Network-on-Chips (NoCs) have recently been proposed due to their inherent low latency and high bandwidth. However, the high static power of the photonic components (e.g. laser source, resonators and waveguides) often results in energy-inefficient architectures. In this paper, we advocate the Energy-Star Photonic Network (ESPN) architecture that optimizes energy utilization via a two-pronged approach: (1) by enabling dynamic resource provisioning, ESPN adapts photonic network resources based on runtime traffic characteristics and (2) by utilizing all-optical adaptive routing, ESPN improves energy efficiency by intelligently exploiting existing network resources without introducing high latency and power hungry auxiliary routing mechanisms. Our evaluation results show that compared to the baseline design, ESPN reduces power and energy consumption under synthetic traffic patterns by 50% and 58% respectively.
{"title":"ESPN: A case for energy-star photonic on-chip network","authors":"Zhongqi Li, Tao Li","doi":"10.1109/ISLPED.2013.6629326","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629326","url":null,"abstract":"Photonic Network-on-Chips (NoCs) have recently been proposed due to their inherent low latency and high bandwidth. However, the high static power of the photonic components (e.g. laser source, resonators and waveguides) often results in energy-inefficient architectures. In this paper, we advocate the Energy-Star Photonic Network (ESPN) architecture that optimizes energy utilization via a two-pronged approach: (1) by enabling dynamic resource provisioning, ESPN adapts photonic network resources based on runtime traffic characteristics and (2) by utilizing all-optical adaptive routing, ESPN improves energy efficiency by intelligently exploiting existing network resources without introducing high latency and power hungry auxiliary routing mechanisms. Our evaluation results show that compared to the baseline design, ESPN reduces power and energy consumption under synthetic traffic patterns by 50% and 58% respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89209438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629299
Tianhao Zheng, Jaeyoung Park, M. Orshansky, M. Erez
In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worst-case duration, the average write energy is significantly reduced by the proposed architecture. We developed a light-weight circuit for fast state change detection and bit-line shutdown and evaluated it using a compact STT-RAM model targeting an implementation in a 16nm technology node. Our analysis indicates that at the required write-error rate the proposed architecture reduces write energy by 87.3%∓99.5% depending on the write direction, and on average achieves 96.5% write energy saving in 16 SPEC CPU 2006 applications compared to conventional design. Compared to the best previously known architecture that exploits stochasticity (verify-on-write), we reduce write energy by approximately 6.5×.
在本文中，我们展示了一种依赖于STT-RAM写操作的随机长尾特性的节能策略。为了摆脱传统的最坏情况方法，对每个单元的写入过程进行持续监控，并在每个单元的状态与写入状态匹配时立即终止。由于平均写持续时间远短于最坏情况持续时间，因此所提出的体系结构显著降低了平均写能量。我们开发了一种用于快速状态变化检测和位线关闭的轻型电路，并使用紧凑型STT-RAM模型对其进行了评估，目标是在16nm技术节点上实现。我们的分析表明，在所需的写入错误率下，根据写入方向，所提出的架构可将写入能量降低87.3% - 99.5%，并且与传统设计相比，在16 SPEC CPU 2006应用程序中平均可实现96.5%的写入能量节省。与先前已知的利用随机性(写时验证)的最佳架构相比，我们将写入能量减少了大约6.5倍。
{"title":"Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring","authors":"Tianhao Zheng, Jaeyoung Park, M. Orshansky, M. Erez","doi":"10.1109/ISLPED.2013.6629299","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629299","url":null,"abstract":"In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worst-case duration, the average write energy is significantly reduced by the proposed architecture. We developed a light-weight circuit for fast state change detection and bit-line shutdown and evaluated it using a compact STT-RAM model targeting an implementation in a 16nm technology node. Our analysis indicates that at the required write-error rate the proposed architecture reduces write energy by 87.3%∓99.5% depending on the write direction, and on average achieves 96.5% write energy saving in 16 SPEC CPU 2006 applications compared to conventional design. Compared to the best previously known architecture that exploits stochasticity (verify-on-write), we reduce write energy by approximately 6.5×.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87013343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629261
S. Samal, Yarui Peng, Yang Zhang, S. Lim
In this paper, we study a 3D IC micro-controller implemented with sub-threshold supply for ultra-low power applications. Our study is based on GDSII layouts of a sub-threshold 8052 micro-controller that consumes 3.6μW power running at 20 KHz clock frequency and 0.4V logic supply. Our study confirms that sub-threshold circuits indeed offer a few orders of magnitude power vs performance tradeoff. In addition, our 3D sub-threshold design reduces the footprint area by 78% and wirelength by 33% compared with the 2D counterpart. Our studies also show that thermal and IR drop issues are negligible in this sub-threshold 3D implementation due to its extreme low power operation. Lastly, we demonstrate the low power and high memory bandwidth advantages of many-core 3D sub-threshold circuits.
{"title":"Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs","authors":"S. Samal, Yarui Peng, Yang Zhang, S. Lim","doi":"10.1109/ISLPED.2013.6629261","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629261","url":null,"abstract":"In this paper, we study a 3D IC micro-controller implemented with sub-threshold supply for ultra-low power applications. Our study is based on GDSII layouts of a sub-threshold 8052 micro-controller that consumes 3.6μW power running at 20 KHz clock frequency and 0.4V logic supply. Our study confirms that sub-threshold circuits indeed offer a few orders of magnitude power vs performance tradeoff. In addition, our 3D sub-threshold design reduces the footprint area by 78% and wirelength by 33% compared with the 2D counterpart. Our studies also show that thermal and IR drop issues are negligible in this sub-threshold 3D implementation due to its extreme low power operation. Lastly, we demonstrate the low power and high memory bandwidth advantages of many-core 3D sub-threshold circuits.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82543065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629263
Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, N. Chang
State-of-the-art electrical energy storage (EES) systems are mainly homogeneous, i.e., they consist of a single type of EES elements. None of the existing EES elements is capable of simultaneously fulfilling all the desired features of an ideal EES system, e.g., high charge/discharge efficiency, high energy density, low cost per unit capacity, long cycle life. A novel technology, i.e., a hybrid EES system that employs heterogeneous EES elements organized in a hierarchy of storage banks and linked by appropriate charge transfer interconnects, has shown great promise in overcoming the aforesaid limitations of conventional EES systems. However, the widespread adoption/deployment of hybrid EES systems is hampered by lack of a hybrid EES system simulator. This paper thus presents SIMES, a powerful and scalable simulator for hybrid EES systems, which provides fast and accurate system simulations, while accounting for key characteristics of various EES elements, power converters, charge transfer interconnect schemes, etc. Experimental results on two different applications (one targeting load shifting for households, the other related to battery rate capacity effect minimization in portable electronic devices) demonstrate the value and usefulness of SIMES for designing energy-aware facilities and products.
{"title":"SIMES: A simulator for hybrid electrical energy storage systems","authors":"Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, N. Chang","doi":"10.1109/ISLPED.2013.6629263","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629263","url":null,"abstract":"State-of-the-art electrical energy storage (EES) systems are mainly homogeneous, i.e., they consist of a single type of EES elements. None of the existing EES elements is capable of simultaneously fulfilling all the desired features of an ideal EES system, e.g., high charge/discharge efficiency, high energy density, low cost per unit capacity, long cycle life. A novel technology, i.e., a hybrid EES system that employs heterogeneous EES elements organized in a hierarchy of storage banks and linked by appropriate charge transfer interconnects, has shown great promise in overcoming the aforesaid limitations of conventional EES systems. However, the widespread adoption/deployment of hybrid EES systems is hampered by lack of a hybrid EES system simulator. This paper thus presents SIMES, a powerful and scalable simulator for hybrid EES systems, which provides fast and accurate system simulations, while accounting for key characteristics of various EES elements, power converters, charge transfer interconnect schemes, etc. Experimental results on two different applications (one targeting load shifting for households, the other related to battery rate capacity effect minimization in portable electronic devices) demonstrate the value and usefulness of SIMES for designing energy-aware facilities and products.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82640013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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