Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629331
Raghavan Kumar, W. Burleson
Physically Unclonable Functions (PUFs) are lightweight cryptographic primitives for generating unique signatures from complex manufacturing variations. In this work, we present a current-based PUF designed using a generalized lithographic simulation framework for improving inter-die and inter-wafer uniqueness. The sensitivity of the circuit to manufacturing variations is enhanced by placing the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. Simulation results show that the litho-aware current based PUF has improved inter- and intra-distance over the conventional current-based PUF. The litho-aware PUF consumes about 0.034 pico joules of energy per response bit, which is substantially better than delay-based PUF implementations.
{"title":"Litho-aware and low power design of a secure current-based physically unclonable function","authors":"Raghavan Kumar, W. Burleson","doi":"10.1109/ISLPED.2013.6629331","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629331","url":null,"abstract":"Physically Unclonable Functions (PUFs) are lightweight cryptographic primitives for generating unique signatures from complex manufacturing variations. In this work, we present a current-based PUF designed using a generalized lithographic simulation framework for improving inter-die and inter-wafer uniqueness. The sensitivity of the circuit to manufacturing variations is enhanced by placing the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. Simulation results show that the litho-aware current based PUF has improved inter- and intra-distance over the conventional current-based PUF. The litho-aware PUF consumes about 0.034 pico joules of energy per response bit, which is substantially better than delay-based PUF implementations.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"58 1","pages":"402-407"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78483410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629257
Cheng-Wen Wu
In the past few years, we have witnessed the energy crisis and the financial tsunami that played an unwanted duo, changing the world in many aspects that affect most of us. While companies are working hard in getting out of the slump, many research organizations are rethinking how their R&D budget should be invested. We consider advanced research activities stressing ultra-low power and energy-efficient circuits and systems a top-priority direction. Among our list of R&D topics are ultra-low voltage circuits and systems, energy-harvesting circuits and systems, 3D integration based on the Through-Silicon-Via (TSV) technology, and normally-off computing technologies. To be successful in integrating the basic technologies developed, a holistic approach should be considered. Therefore, in addition to introduction and discussion of the above research topics at ITRI, I will also discuss a system-level modeling and evaluation platform, emphasizing power/energy efficiency.
{"title":"Holistic approach to low-power system design","authors":"Cheng-Wen Wu","doi":"10.1109/ISLPED.2013.6629257","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629257","url":null,"abstract":"In the past few years, we have witnessed the energy crisis and the financial tsunami that played an unwanted duo, changing the world in many aspects that affect most of us. While companies are working hard in getting out of the slump, many research organizations are rethinking how their R&D budget should be invested. We consider advanced research activities stressing ultra-low power and energy-efficient circuits and systems a top-priority direction. Among our list of R&D topics are ultra-low voltage circuits and systems, energy-harvesting circuits and systems, 3D integration based on the Through-Silicon-Via (TSV) technology, and normally-off computing technologies. To be successful in integrating the basic technologies developed, a holistic approach should be considered. Therefore, in addition to introduction and discussion of the above research topics at ITRI, I will also discuss a system-level modeling and evaluation platform, emphasizing power/energy efficiency.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"90 1","pages":"2"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72974724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629307
Yu Chen, Mingoo Seok, S. Nowick
Asynchronous dynamic pipelines are increasingly being used, including in recent commercial design flows, since they simultaneously provide high-performance, clock-free operation and delay-insensitive communication. While they also show promise for energy-efficient ultra-low-voltage circuits, with always-on keepers, these circuits exhibit severe robustness issues. In this paper, an adaptive keeper solution is introduced, to eliminate write contention issues. Arbitrary unknown data rates and congestion must be safely handled, without a reference clock, hence conventional solutions for synchronous design cannot be applied. The proposed method, demonstrated in two widely-used pipelines (PS0, PCHB), directly addresses the asynchronous contention issue by dynamic monitoring of neighboring traffic at each pipeline stage. Simulations of a pipelined ripple-carry adder show correct operation at 0.3 V with energy improvements of up to 4.4× compared to a non-adaptive design. In addition, the approach also improves pipeline throughput by 24.4% and 17.4% at 0.6 V and nominal 1.0 V, respectively.
{"title":"Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control","authors":"Yu Chen, Mingoo Seok, S. Nowick","doi":"10.1109/ISLPED.2013.6629307","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629307","url":null,"abstract":"Asynchronous dynamic pipelines are increasingly being used, including in recent commercial design flows, since they simultaneously provide high-performance, clock-free operation and delay-insensitive communication. While they also show promise for energy-efficient ultra-low-voltage circuits, with always-on keepers, these circuits exhibit severe robustness issues. In this paper, an adaptive keeper solution is introduced, to eliminate write contention issues. Arbitrary unknown data rates and congestion must be safely handled, without a reference clock, hence conventional solutions for synchronous design cannot be applied. The proposed method, demonstrated in two widely-used pipelines (PS0, PCHB), directly addresses the asynchronous contention issue by dynamic monitoring of neighboring traffic at each pipeline stage. Simulations of a pipelined ripple-carry adder show correct operation at 0.3 V with energy improvements of up to 4.4× compared to a non-adaptive design. In addition, the approach also improves pipeline throughput by 24.4% and 17.4% at 0.6 V and nominal 1.0 V, respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"25 1","pages":"267-272"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80181890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629279
Mark Buckler, W. Burleson, G. Sadowski
After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given system's power budget. This brief paper and accompanying presentation discuss what options are available to designers who need to reduce NoC power consumption, their benefits, and their limitations. Techniques discussed here include general NoC system design as well as disruptive interconnect mediums and their associated strategies.
{"title":"Low-power Networks-on-Chip: Progress and remaining challenges","authors":"Mark Buckler, W. Burleson, G. Sadowski","doi":"10.1109/ISLPED.2013.6629279","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629279","url":null,"abstract":"After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given system's power budget. This brief paper and accompanying presentation discuss what options are available to designers who need to reduce NoC power consumption, their benefits, and their limitations. Techniques discussed here include general NoC system design as well as disruptive interconnect mediums and their associated strategies.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"1 1","pages":"132-134"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83617095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629330
Emily Bragg, Marisabel Guevara, Benjamin C. Lee
Today's largest datacenters dissipate megawatts of power. Efficiency is rapidly becoming the primary determinant of datacenter capability. To understand microarchitectural factors that affect efficiency, we must study datacenter workloads.
{"title":"Understanding query complexity and its implications for energy-efficient web search","authors":"Emily Bragg, Marisabel Guevara, Benjamin C. Lee","doi":"10.1109/ISLPED.2013.6629330","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629330","url":null,"abstract":"Today's largest datacenters dissipate megawatts of power. Efficiency is rapidly becoming the primary determinant of datacenter capability. To understand microarchitectural factors that affect efficiency, we must study datacenter workloads.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"12 1","pages":"401"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81019173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629262
Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar
We propose a framework that enables intensive computation on ultra-low power devices with discontinuous energy-harvesting supplies. We devise an optimization algorithm that efficiently partitions the applications into smaller computational steps during high-level synthesis. Our system finds low-overhead checkpoints that minimize recomputation cost due to power losses, then inserts the checkpoints at the design's registertransfer level. The checkpointing rate is automatically adapted to the source's realtime behavior. We evaluate our mechanisms on a battery-less RF energy-harvester platform. Extensive experiments targeting applications in medical implant devices demonstrate our approach's ability to successfully execute complex computations for various supply patterns with low time, energy, and area overheads.
{"title":"Automated checkpointing for enabling intensive applications on energy harvesting devices","authors":"Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar","doi":"10.1109/ISLPED.2013.6629262","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629262","url":null,"abstract":"We propose a framework that enables intensive computation on ultra-low power devices with discontinuous energy-harvesting supplies. We devise an optimization algorithm that efficiently partitions the applications into smaller computational steps during high-level synthesis. Our system finds low-overhead checkpoints that minimize recomputation cost due to power losses, then inserts the checkpoints at the design's registertransfer level. The checkpointing rate is automatically adapted to the source's realtime behavior. We evaluate our mechanisms on a battery-less RF energy-harvester platform. Extensive experiments targeting applications in medical implant devices demonstrate our approach's ability to successfully execute complex computations for various supply patterns with low time, energy, and area overheads.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"95 1","pages":"27-32"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86985132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose new techniques for post-silicon power mapping and modeling of multi-core processors using infrared imaging and performance counter measurements. An accurate finite-element modeling framework is used to capture the relationship between temperature and power, while compensating for the artifacts introduced from substituting traditional heat removal mechanisms with oil-based infrared-transparent cooling mechanisms. We use thermal conditioning techniques to build leakage power models for the die. Utilizing the power maps identified from infrared mapping, we develop empirical power models for different processor blocks based on the measurements from the performance monitoring counters (PMCs), and utilize the PMC-based models to analyze the transient power consumption. In our experiments, we capture thermal images from a quad-core processor under different workload conditions, and then we reconstruct the dynamic and leakage power maps for different blocks. Our results show good accuracy in mapping and modeling, revealing good insights into the trends of power consumption in multi-core processors.
{"title":"Power mapping and modeling of multi-core processors","authors":"K. Dev, Abdullah Nazma Nowroz, S. Reda","doi":"10.5555/2648668.2648680","DOIUrl":"https://doi.org/10.5555/2648668.2648680","url":null,"abstract":"We propose new techniques for post-silicon power mapping and modeling of multi-core processors using infrared imaging and performance counter measurements. An accurate finite-element modeling framework is used to capture the relationship between temperature and power, while compensating for the artifacts introduced from substituting traditional heat removal mechanisms with oil-based infrared-transparent cooling mechanisms. We use thermal conditioning techniques to build leakage power models for the die. Utilizing the power maps identified from infrared mapping, we develop empirical power models for different processor blocks based on the measurements from the performance monitoring counters (PMCs), and utilize the PMC-based models to analyze the transient power consumption. In our experiments, we capture thermal images from a quad-core processor under different workload conditions, and then we reconstruct the dynamic and leakage power maps for different blocks. Our results show good accuracy in mapping and modeling, revealing good insights into the trends of power consumption in multi-core processors.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"13 1","pages":"39-44"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73933699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629292
Vignyan Reddy Kothinti Naresh, S. Gilani, Erika Gunadi, N. Kim, M. Schulte, Mikko H. Lipasti
The height of the dynamic dependence graph of a program, as executed by a processor, determines the minimum bound on the execution time. This height can be decreased by reducing the effective execution latency of operations that form dependence chains in the graph. In this paper, we propose a technique called REEL to reduce overall latency of chains of dependent floating point (FP) operations by increasing the throughput of computation. REEL comprises of a high-throughput floating point unit (HFP) that allows early issue of an FP Add that is dependent on another FP Add or FP Multiply. This is complemented by instruction scheduler modifications that allow early issue of dependent FP Adds, and a novel checker logic that corrects any precision errors. Unlike conventional static operation fusion, like fused Multiply-Add (FMA), there are no changes to the instruction set to enable utilization of the new hardware, and no recompilation is necessary. Furthermore, unlike ISA-level FMA, our technique produces results that are bit compatible while boosting performance of Add-Add dependence pairs in addition to Multiply-Add pairs. Our evaluation of REEL using CFP2006 benchmarks shows an average performance gain of 7.6% and maximum performance gain of 17% while consuming 1.2% lower energy.
{"title":"REEL: Reducing effective execution latency of floating point operations","authors":"Vignyan Reddy Kothinti Naresh, S. Gilani, Erika Gunadi, N. Kim, M. Schulte, Mikko H. Lipasti","doi":"10.1109/ISLPED.2013.6629292","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629292","url":null,"abstract":"The height of the dynamic dependence graph of a program, as executed by a processor, determines the minimum bound on the execution time. This height can be decreased by reducing the effective execution latency of operations that form dependence chains in the graph. In this paper, we propose a technique called REEL to reduce overall latency of chains of dependent floating point (FP) operations by increasing the throughput of computation. REEL comprises of a high-throughput floating point unit (HFP) that allows early issue of an FP Add that is dependent on another FP Add or FP Multiply. This is complemented by instruction scheduler modifications that allow early issue of dependent FP Adds, and a novel checker logic that corrects any precision errors. Unlike conventional static operation fusion, like fused Multiply-Add (FMA), there are no changes to the instruction set to enable utilization of the new hardware, and no recompilation is necessary. Furthermore, unlike ISA-level FMA, our technique produces results that are bit compatible while boosting performance of Add-Add dependence pairs in addition to Multiply-Add pairs. Our evaluation of REEL using CFP2006 benchmarks shows an average performance gain of 7.6% and maximum performance gain of 17% while consuming 1.2% lower energy.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"75 1","pages":"187-192"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72718154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629322
Ming Fan, Vivek Chaturvedi, Shi Sha, Gang Quan
Energy minimization is a critical issue and challenge when considering the cyclic dependency of leakage power and temperature as IC technology reaches deep sub-micron level. In this paper, we present an analytical method to calculate the energy consumption efficiently and effectively for a given voltage schedule on a multi-core platform, with the leakage/temperature dependency taken into consideration. Our experiments show that the proposed method can achieve a speedup of 15 times compared with the numerical method, with a relative error of no more than 1.5%.
{"title":"An analytical solution for multi-core energy calculation with consideration of leakage and temperature dependency","authors":"Ming Fan, Vivek Chaturvedi, Shi Sha, Gang Quan","doi":"10.1109/ISLPED.2013.6629322","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629322","url":null,"abstract":"Energy minimization is a critical issue and challenge when considering the cyclic dependency of leakage power and temperature as IC technology reaches deep sub-micron level. In this paper, we present an analytical method to calculate the energy consumption efficiently and effectively for a given voltage schedule on a multi-core platform, with the leakage/temperature dependency taken into consideration. Our experiments show that the proposed method can achieve a speedup of 15 times compared with the numerical method, with a relative error of no more than 1.5%.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"1 1","pages":"353-358"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75772833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629261
S. Samal, Yarui Peng, Yang Zhang, S. Lim
In this paper, we study a 3D IC micro-controller implemented with sub-threshold supply for ultra-low power applications. Our study is based on GDSII layouts of a sub-threshold 8052 micro-controller that consumes 3.6μW power running at 20 KHz clock frequency and 0.4V logic supply. Our study confirms that sub-threshold circuits indeed offer a few orders of magnitude power vs performance tradeoff. In addition, our 3D sub-threshold design reduces the footprint area by 78% and wirelength by 33% compared with the 2D counterpart. Our studies also show that thermal and IR drop issues are negligible in this sub-threshold 3D implementation due to its extreme low power operation. Lastly, we demonstrate the low power and high memory bandwidth advantages of many-core 3D sub-threshold circuits.
{"title":"Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs","authors":"S. Samal, Yarui Peng, Yang Zhang, S. Lim","doi":"10.1109/ISLPED.2013.6629261","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629261","url":null,"abstract":"In this paper, we study a 3D IC micro-controller implemented with sub-threshold supply for ultra-low power applications. Our study is based on GDSII layouts of a sub-threshold 8052 micro-controller that consumes 3.6μW power running at 20 KHz clock frequency and 0.4V logic supply. Our study confirms that sub-threshold circuits indeed offer a few orders of magnitude power vs performance tradeoff. In addition, our 3D sub-threshold design reduces the footprint area by 78% and wirelength by 33% compared with the 2D counterpart. Our studies also show that thermal and IR drop issues are negligible in this sub-threshold 3D implementation due to its extreme low power operation. Lastly, we demonstrate the low power and high memory bandwidth advantages of many-core 3D sub-threshold circuits.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"30 1","pages":"21-26"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82543065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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