Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273480
Naresh R Shanbhag
Computing platforms operating at the limits of energy-efficiency need to contend with the issue of robustness. This energy vs. robustness trade-off is fundamental in such systems. This talk will describe a Shannon-inspired framework referred to as statistical information processing (SIP). SIP navigates the energy vs. robustness trade-off by treating the problem of energy-efficient computing as one of information processing on low-SNR and unreliable nanoscale device/circuit fabrics. In doing do, SIP seeks to transform computing from its von Neumann roots in data processing to a Shannon-inspired foundation for information processing. Key elements of SIP are the use of information-based metrics, a stochastic low-SNR circuit fabric, and statistical error compensation techniques based on estimation and detection theory, and machine learning. SIP has been used for designing energy-efficient and robust computation, communication, storage, and mixed-signal analog front-ends. This talk will conclude with a brief overview of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi-university research center, focused on developing a Shannon/brain-inspired foundation for information processing on CMOS and beyond CMOS nanoscale fabrics.
{"title":"Statistical information processing: Computing for the nanoscale era","authors":"Naresh R Shanbhag","doi":"10.1109/ISLPED.2015.7273480","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273480","url":null,"abstract":"Computing platforms operating at the limits of energy-efficiency need to contend with the issue of robustness. This energy vs. robustness trade-off is fundamental in such systems. This talk will describe a Shannon-inspired framework referred to as statistical information processing (SIP). SIP navigates the energy vs. robustness trade-off by treating the problem of energy-efficient computing as one of information processing on low-SNR and unreliable nanoscale device/circuit fabrics. In doing do, SIP seeks to transform computing from its von Neumann roots in data processing to a Shannon-inspired foundation for information processing. Key elements of SIP are the use of information-based metrics, a stochastic low-SNR circuit fabric, and statistical error compensation techniques based on estimation and detection theory, and machine learning. SIP has been used for designing energy-efficient and robust computation, communication, storage, and mixed-signal analog front-ends. This talk will conclude with a brief overview of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi-university research center, focused on developing a Shannon/brain-inspired foundation for information processing on CMOS and beyond CMOS nanoscale fabrics.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75681231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629302
Boxun Li, Yi Shan, Miao Hu, Yu Wang, Yiran Chen, Huazhong Yang
The cessation of Moore's Law has limited further improvements in power efficiency. In recent years, the physical realization of the memristor has demonstrated a promising solution to ultra-integrated hardware realization of neural networks, which can be leveraged for better performance and power efficiency gains. In this work, we introduce a power efficient framework for approximated computations by taking advantage of the memristor-based multilayer neural networks. A programmable memristor approximated computation unit (Memristor ACU) is introduced first to accelerate approximated computation and a memristor-based approximated computation framework with scalability is proposed on top of the Memristor ACU. We also introduce a parameter configuration algorithm of the Memristor ACU and a feedback state tuning circuit to program the Memristor ACU effectively. Our simulation results show that the maximum error of the Memristor ACU for 6 common complex functions is only 1.87% while the state tuning circuit can achieve 12-bit precision. The implementation of HMAX model atop our proposed memristor-based approximated computation framework demonstrates 22× power efficiency improvements than its pure digital implementation counterpart.
{"title":"Memristor-based approximated computation","authors":"Boxun Li, Yi Shan, Miao Hu, Yu Wang, Yiran Chen, Huazhong Yang","doi":"10.1109/ISLPED.2013.6629302","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629302","url":null,"abstract":"The cessation of Moore's Law has limited further improvements in power efficiency. In recent years, the physical realization of the memristor has demonstrated a promising solution to ultra-integrated hardware realization of neural networks, which can be leveraged for better performance and power efficiency gains. In this work, we introduce a power efficient framework for approximated computations by taking advantage of the memristor-based multilayer neural networks. A programmable memristor approximated computation unit (Memristor ACU) is introduced first to accelerate approximated computation and a memristor-based approximated computation framework with scalability is proposed on top of the Memristor ACU. We also introduce a parameter configuration algorithm of the Memristor ACU and a feedback state tuning circuit to program the Memristor ACU effectively. Our simulation results show that the maximum error of the Memristor ACU for 6 common complex functions is only 1.87% while the state tuning circuit can achieve 12-bit precision. The implementation of HMAX model atop our proposed memristor-based approximated computation framework demonstrates 22× power efficiency improvements than its pure digital implementation counterpart.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74578326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629267
L. Clark, S. Leshner, G. Tien
In this paper, we describe a six-transistor static random access memory (SRAM) cell optimization methodology for transistors with significantly improved matching, while maintaining compatibility with the baseline design. We briefly describe the reduced AVT transistors and show that they allow substantially improved minimum SRAM operating voltage (Vmin) and improved array leakage. Using an efficient design of experiments (DOE) factorial as a pseudo-Monte Carlo generator, points on the tail of the distribution are directly simulated. The highly efficient method is shown to allow optimization and `what if' scenario investigations. Simulation and silicon results on a 65-nm process as well as simulation results on a 28-nm process are shown.
{"title":"SRAM cell optimization for low AVT transistors","authors":"L. Clark, S. Leshner, G. Tien","doi":"10.1109/ISLPED.2013.6629267","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629267","url":null,"abstract":"In this paper, we describe a six-transistor static random access memory (SRAM) cell optimization methodology for transistors with significantly improved matching, while maintaining compatibility with the baseline design. We briefly describe the reduced AVT transistors and show that they allow substantially improved minimum SRAM operating voltage (Vmin) and improved array leakage. Using an efficient design of experiments (DOE) factorial as a pseudo-Monte Carlo generator, points on the tail of the distribution are directly simulated. The highly efficient method is shown to allow optimization and `what if' scenario investigations. Simulation and silicon results on a 65-nm process as well as simulation results on a 28-nm process are shown.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75096222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) has shown potential for main memory storage but also computing capability. In this paper, the domain-wall nanowire is studied for a memory-based computing platform towards ultra-low-power big-data processing. One domain-wall nanowire based logic-in-memory architecture is proposed for big-data processing, where the domain-wall nanowire memory is deployed as main memory for data storage as well as XOR-logic for comparison and addition operations. The domain-wall nanowire based logic-in-memory circuits are evaluated by SPICE-level verifications. Further evaluated by applications of general-purpose SPEC2006 benchmark and also web-searching oriented Phoenix benchmark, the proposed computing platform can exhibit a significant power saving on both main memory and ALU under the similar performance when compared to CMOS based designs.
{"title":"An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices","authors":"Yuhao Wang, Hao Yu","doi":"10.5555/2648668.2648748","DOIUrl":"https://doi.org/10.5555/2648668.2648748","url":null,"abstract":"As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) has shown potential for main memory storage but also computing capability. In this paper, the domain-wall nanowire is studied for a memory-based computing platform towards ultra-low-power big-data processing. One domain-wall nanowire based logic-in-memory architecture is proposed for big-data processing, where the domain-wall nanowire memory is deployed as main memory for data storage as well as XOR-logic for comparison and addition operations. The domain-wall nanowire based logic-in-memory circuits are evaluated by SPICE-level verifications. Further evaluated by applications of general-purpose SPEC2006 benchmark and also web-searching oriented Phoenix benchmark, the proposed computing platform can exhibit a significant power saving on both main memory and ALU under the similar performance when compared to CMOS based designs.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81631046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yan Li, Kun Wang, Qi Guo, Xin Li, Xiaochen Zhang, Guancheng Chen, Tao Liu, Jian Li
MapReduce plays an critical role in finding insights in Big Data. The performance optimization of MapReduce programs is challenging because it requires a comprehensive understanding of the whole system including both hardware layers (processors, storages, networks and etc), and software stacks (operating systems, JVM, runtime, applications and etc). However, most of the existing performance tuning and optimization are based on empirical and heuristic attempts. It remains a blank on how to build a systematical framework which breaks the boundary of multiple layers for performance optimization. In this paper, we propose a performance evaluation framework by correlating performance metrics from different layers, which provides insights to efficiently pinpoint the performance issue. This framework is composed of a series of predefined patterns. Each pattern indicates one or more potential issues. The behavior of a MapReduce program is mapped to the corresponding resource utilization. The framework provides a holistic approach which allows users at different levels of experience to conduct MapReduce program performance optimization. We use Terasort benchmark running on a 10-node Power7R2 cluster as a real case to show how this framework improves the performance. By this framework, we finally get the Terasort result improved from 47 mins to less than 8 mins. In addition to the best practice on performance tuning, several key findings are summarized as valuable workload analysis for JVM, MapReduce runtime and application design.
{"title":"Breaking the boundary for whole-system performance optimization of big data","authors":"Yan Li, Kun Wang, Qi Guo, Xin Li, Xiaochen Zhang, Guancheng Chen, Tao Liu, Jian Li","doi":"10.5555/2648668.2648699","DOIUrl":"https://doi.org/10.5555/2648668.2648699","url":null,"abstract":"MapReduce plays an critical role in finding insights in Big Data. The performance optimization of MapReduce programs is challenging because it requires a comprehensive understanding of the whole system including both hardware layers (processors, storages, networks and etc), and software stacks (operating systems, JVM, runtime, applications and etc). However, most of the existing performance tuning and optimization are based on empirical and heuristic attempts. It remains a blank on how to build a systematical framework which breaks the boundary of multiple layers for performance optimization. In this paper, we propose a performance evaluation framework by correlating performance metrics from different layers, which provides insights to efficiently pinpoint the performance issue. This framework is composed of a series of predefined patterns. Each pattern indicates one or more potential issues. The behavior of a MapReduce program is mapped to the corresponding resource utilization. The framework provides a holistic approach which allows users at different levels of experience to conduct MapReduce program performance optimization. We use Terasort benchmark running on a 10-node Power7R2 cluster as a real case to show how this framework improves the performance. By this framework, we finally get the Terasort result improved from 47 mins to less than 8 mins. In addition to the best practice on performance tuning, several key findings are summarized as valuable workload analysis for JVM, MapReduce runtime and application design.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84956614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629283
G. Salis
The emerging ability to measure and control electron spins in nano-structured materials down to the level of single spins is at the heart of the research field of spintronics, with potential applications in logic and quantum computation. In current semiconductor-based logic devices, the electron spin is a quantity that is mostly neglected. The switching functionality of a conventional field-effect transistor is based on charging a channel region with electrons. For a given on/off ratio of the source-drain current, the switching requires a minimum voltage swing related to the thermal energy, which sets a lower limit on the active power consumption of the device. Such a principal limitation is not present if the spin direction of electrons is switched. This observation has triggered huge interest in spintronics as a low-power alternative for logic devices. With the example of existing spintronics device concept, the challenges for using spin switches in logic applications will be discussed. Very large spin filtering efficiencies are needed to use a spin switch as a drop-in replacement for FET-based current switches, setting demanding requirements for the processes of spin injection and detection. An alternative approach is to encode the digital information directly into the spin state and omit excess spin-to-charge conversion, which however requires the development of spin amplification to achieve gain in the spin domain. Many spintronics device concepts comprise nonmagnetic regions where non-equilibrium spin polarization is switched by electrical fields. There, the spins have to be processed within the respective spin lifetime. We will discuss how spin-orbit interaction limits the spin lifetime but at the same time is needed for electrical spin switching. Experimental results based on time-resolved magneto-optical Kerr rotation will be shown that demonstrate fast switching of spins in GaAs-based semiconductor quantum structures with specially engineered spin-orbit interaction where the influence on the spin lifetime is lifted.
{"title":"Semiconductor spintronics: switching spins at low voltage","authors":"G. Salis","doi":"10.1109/ISLPED.2013.6629283","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629283","url":null,"abstract":"The emerging ability to measure and control electron spins in nano-structured materials down to the level of single spins is at the heart of the research field of spintronics, with potential applications in logic and quantum computation. In current semiconductor-based logic devices, the electron spin is a quantity that is mostly neglected. The switching functionality of a conventional field-effect transistor is based on charging a channel region with electrons. For a given on/off ratio of the source-drain current, the switching requires a minimum voltage swing related to the thermal energy, which sets a lower limit on the active power consumption of the device. Such a principal limitation is not present if the spin direction of electrons is switched. This observation has triggered huge interest in spintronics as a low-power alternative for logic devices.\u0000 With the example of existing spintronics device concept, the challenges for using spin switches in logic applications will be discussed. Very large spin filtering efficiencies are needed to use a spin switch as a drop-in replacement for FET-based current switches, setting demanding requirements for the processes of spin injection and detection. An alternative approach is to encode the digital information directly into the spin state and omit excess spin-to-charge conversion, which however requires the development of spin amplification to achieve gain in the spin domain.\u0000 Many spintronics device concepts comprise nonmagnetic regions where non-equilibrium spin polarization is switched by electrical fields. There, the spins have to be processed within the respective spin lifetime. We will discuss how spin-orbit interaction limits the spin lifetime but at the same time is needed for electrical spin switching. Experimental results based on time-resolved magneto-optical Kerr rotation will be shown that demonstrate fast switching of spins in GaAs-based semiconductor quantum structures with specially engineered spin-orbit interaction where the influence on the spin lifetime is lifted.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80448700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629258
Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang
The large Register File (RF) in General Purpose Graphic Processing Units (GPGPUs) demands tremendous chip area and energy consumption. For a sustainable growth of the size of RF in future GPGPUs, emerging on-chip memory technologies such as embedded-DRAM (eDRAM) have been proposed to replace the conventional SRAM for higher density and lower leakage but with the possible penalty from the periodic refresh operations. This paper explicitly shows that the refresh penalty can be effectively mitigated by leveraging the uniqueness of GPGPU operations. A compiler assisted refresh rescheduling policy can greatly reduce the refresh overhead for maintaining the correctness of the RF operations. The proposed scheme adequately exploits the features in both architecture and compilation, and delivers comparable performance to the SRAM counterpart. At the same time, the energy savings via the removal of large SRAM leakage well compensate for the additional refresh energy. This study promotes the eDRAM-based RF as a promising alternative that enables larger capacity and better power efficiency for future GPGPUs.
{"title":"Compiler assisted dynamic register file in GPGPU","authors":"Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang","doi":"10.1109/ISLPED.2013.6629258","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629258","url":null,"abstract":"The large Register File (RF) in General Purpose Graphic Processing Units (GPGPUs) demands tremendous chip area and energy consumption. For a sustainable growth of the size of RF in future GPGPUs, emerging on-chip memory technologies such as embedded-DRAM (eDRAM) have been proposed to replace the conventional SRAM for higher density and lower leakage but with the possible penalty from the periodic refresh operations. This paper explicitly shows that the refresh penalty can be effectively mitigated by leveraging the uniqueness of GPGPU operations. A compiler assisted refresh rescheduling policy can greatly reduce the refresh overhead for maintaining the correctness of the RF operations. The proposed scheme adequately exploits the features in both architecture and compilation, and delivers comparable performance to the SRAM counterpart. At the same time, the energy savings via the removal of large SRAM leakage well compensate for the additional refresh energy. This study promotes the eDRAM-based RF as a promising alternative that enables larger capacity and better power efficiency for future GPGPUs.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78967576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629303
J. Liou
Electrostatic discharge (ESD) is a process in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the object within a very short period of time [1-2]. When a microchip or electronic system is subject to an ESD event, the huge ESD-induced current can likely damage the microchip and cause malfunction to the electronic system if the heat generated in the object cannot be dissipated quickly enough. It is estimated that about 35% of all damaged microchips are ESD related, resulting in a revenue loss of several hundred million dollars in the global semiconductor industry every year [3]. The continuing diminishing in the size of MOS devices makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical component to the successful development of the CMOS-based integrated circuits [4-7].
{"title":"Challenges on designing electrostatic discharge protection solutions for low power electronics","authors":"J. Liou","doi":"10.1109/ISLPED.2013.6629303","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629303","url":null,"abstract":"Electrostatic discharge (ESD) is a process in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the object within a very short period of time [1-2]. When a microchip or electronic system is subject to an ESD event, the huge ESD-induced current can likely damage the microchip and cause malfunction to the electronic system if the heat generated in the object cannot be dissipated quickly enough. It is estimated that about 35% of all damaged microchips are ESD related, resulting in a revenue loss of several hundred million dollars in the global semiconductor industry every year [3]. The continuing diminishing in the size of MOS devices makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical component to the successful development of the CMOS-based integrated circuits [4-7].","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87069360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629316
S. Xi, Marisabel Guevara, Jared Nelson, Patrick Pensabene, Benjamin C. Lee
Increasing demands on datacenter computing prompts research in energy-efficient warehouse scale systems. In one approach, server activation policies invoke low-power sleep states but the power state transition latency must be small to produce effective energy savings. Chrome OS and Arch Linux require 50ms and 650ms, respectively, to enter sleep states. These states consume merely 4-6% of nominal power. By analyzing the critical path, we propose strategies for selecting hardware components and optimizing kernel resume sequences to make datacenter server activation viable. With fast transitions, server activation can provide better performance at lower energy than dynamic voltage and frequency scaling.
{"title":"Understanding the critical path in power state transition latencies","authors":"S. Xi, Marisabel Guevara, Jared Nelson, Patrick Pensabene, Benjamin C. Lee","doi":"10.1109/ISLPED.2013.6629316","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629316","url":null,"abstract":"Increasing demands on datacenter computing prompts research in energy-efficient warehouse scale systems. In one approach, server activation policies invoke low-power sleep states but the power state transition latency must be small to produce effective energy savings. Chrome OS and Arch Linux require 50ms and 650ms, respectively, to enter sleep states. These states consume merely 4-6% of nominal power. By analyzing the critical path, we propose strategies for selecting hardware components and optimizing kernel resume sequences to make datacenter server activation viable. With fast transitions, server activation can provide better performance at lower energy than dynamic voltage and frequency scaling.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90584357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-04DOI: 10.1109/ISLPED.2013.6629260
Seung-Ho Ok, Kyeong-Ryeol Bae, S. Lim, Byungin Moon
This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.
{"title":"Design and analysis of 3D IC-based low power stereo matching processors","authors":"Seung-Ho Ok, Kyeong-Ryeol Bae, S. Lim, Byungin Moon","doi":"10.1109/ISLPED.2013.6629260","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629260","url":null,"abstract":"This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86981746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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