Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243920
Björn Breidegard, P. Andersson
BBDS, an interactive graphical design tool for developing clock cycle true system models, is described. A design idea is entered through graphical interaction based on the Werner diagram. All important decisions about scheduling and allocation of operations are visually explicit. The design can rapidly be verified through simulation, timing analysis, area estimation and prototyping in programmable gate arrays. This allows very fast evaluation of an architectural idea, and allows for a series of fast iterative design improvements, BBDS also enforces a set of formally defined rules based on attributes of signals and component connectors to guarantee consistency of the clocking scheme. Both standard components and software can be accommodated. BBDS can be used to investigate the partitioning of a computer system into software and hardware, and is based on automatic synthesis with a user selectable target library.<>
{"title":"BBDS-a design tool for architectural evaluation and rapid prototyping of performance critical digital systems","authors":"Björn Breidegard, P. Andersson","doi":"10.1109/IWRSP.1992.243920","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243920","url":null,"abstract":"BBDS, an interactive graphical design tool for developing clock cycle true system models, is described. A design idea is entered through graphical interaction based on the Werner diagram. All important decisions about scheduling and allocation of operations are visually explicit. The design can rapidly be verified through simulation, timing analysis, area estimation and prototyping in programmable gate arrays. This allows very fast evaluation of an architectural idea, and allows for a series of fast iterative design improvements, BBDS also enforces a set of formally defined rules based on attributes of signals and component connectors to guarantee consistency of the clocking scheme. Both standard components and software can be accommodated. BBDS can be used to investigate the partitioning of a computer system into software and hardware, and is based on automatic synthesis with a user selectable target library.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131323359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243909
S. Suh, M. Tanik, D. Frailey
Several commercial expert system shells provide knowledge engineers with the capability of developing expert system applications, but are not able to meet the size constraints or provide the run-time performance needed to address problems associated with delivery of embedded real-time applications. In addition, there is no provision to provide deliverable code in Ada, a requirement for many US DoD systems. The embedded consultant project addresses these issues by knowledge-base size reduction by means of code optimization techniques, and by an inference engine, written in Ada, designed for real-time applications. A new rapid prototyping approach for real-time applications is described. The methodology is based on the reuse of existing software components. The approach, and the significance of the work are discussed.<>
{"title":"Requirements specification for a real-time embedded expert system for rapid prototyping","authors":"S. Suh, M. Tanik, D. Frailey","doi":"10.1109/IWRSP.1992.243909","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243909","url":null,"abstract":"Several commercial expert system shells provide knowledge engineers with the capability of developing expert system applications, but are not able to meet the size constraints or provide the run-time performance needed to address problems associated with delivery of embedded real-time applications. In addition, there is no provision to provide deliverable code in Ada, a requirement for many US DoD systems. The embedded consultant project addresses these issues by knowledge-base size reduction by means of code optimization techniques, and by an inference engine, written in Ada, designed for real-time applications. A new rapid prototyping approach for real-time applications is described. The methodology is based on the reuse of existing software components. The approach, and the significance of the work are discussed.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131732430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243906
D. Mulcare
A system-level prototyping method has been developed for modeling the dynamics of concurrent real-time systems. This approach is based on higher-level statecharts, which embody object-based extensions to basic statecharts. To exemplify this method, a global communication mechanism is prototyped for a real-time multicomputer system that executes a single logical multitasking program. Since this prototype is intended to verify real-time concurrency logic, calibrate performance, and ensure safety, it includes a global virtual time base as a statechart subgraph. The prototyping process consists of capturing the system-level communication architecture in a higher-level statechart, and then translating it to an Ada multitasking program. A characteristic software architecture implicit in higher-level statecharts, known as a mutual agents architecture, appears to be suitable for an automated prototyping environment.<>
{"title":"Higher-level statecharts for prototyping architectural dynamics","authors":"D. Mulcare","doi":"10.1109/IWRSP.1992.243906","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243906","url":null,"abstract":"A system-level prototyping method has been developed for modeling the dynamics of concurrent real-time systems. This approach is based on higher-level statecharts, which embody object-based extensions to basic statecharts. To exemplify this method, a global communication mechanism is prototyped for a real-time multicomputer system that executes a single logical multitasking program. Since this prototype is intended to verify real-time concurrency logic, calibrate performance, and ensure safety, it includes a global virtual time base as a statechart subgraph. The prototyping process consists of capturing the system-level communication architecture in a higher-level statechart, and then translating it to an Ada multitasking program. A characteristic software architecture implicit in higher-level statecharts, known as a mutual agents architecture, appears to be suitable for an automated prototyping environment.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131290721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243916
G. Bucci, E. Vicario
The design and implementation of a tool for the construction of distributed systems are described. This tool is based on a specification model which extends ordinary Petri nets to include functional and structural concepts. Functional extensions give the model specification completeness, whereas structuring extensions support the organization of the system under development into a set of message passing modules. The augmented model is named communicating Petri net (CmPN). After an introduction to communicating Petri nets, an outline of the software lifecycle activities enforced by the tool under development is given. Two different methods for automatic code generation are expounded and compared in terms of both computational run-time overhead and code dimension (in the case of an example comprised of four CmPNs).<>
{"title":"Rapid prototyping through communicating Petri nets","authors":"G. Bucci, E. Vicario","doi":"10.1109/IWRSP.1992.243916","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243916","url":null,"abstract":"The design and implementation of a tool for the construction of distributed systems are described. This tool is based on a specification model which extends ordinary Petri nets to include functional and structural concepts. Functional extensions give the model specification completeness, whereas structuring extensions support the organization of the system under development into a set of message passing modules. The augmented model is named communicating Petri net (CmPN). After an introduction to communicating Petri nets, an outline of the software lifecycle activities enforced by the tool under development is given. Two different methods for automatic code generation are expounded and compared in terms of both computational run-time overhead and code dimension (in the case of an example comprised of four CmPNs).<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"11 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132816415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243898
M. Lindsey
Automated aids to generating test procedures for electronic systems from top-level system specifications are described. A five-phase design methodology which incorporates VHSIC description language, (VHDL) modeling allows concurrent development of complex systems and associated test procedures. The methodology proceeds in a top-down fashion, progressively adding design detail in each phase. A proprietary software tool combined with VHDL modeling allow test information to automatically migrate through each phase. This allows system implementation to be verified against the original top-level specification. This method of automated test procedure generation provides significant insight into system operation.<>
{"title":"Automatic test procedure generation from system specifications","authors":"M. Lindsey","doi":"10.1109/IWRSP.1992.243898","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243898","url":null,"abstract":"Automated aids to generating test procedures for electronic systems from top-level system specifications are described. A five-phase design methodology which incorporates VHSIC description language, (VHDL) modeling allows concurrent development of complex systems and associated test procedures. The methodology proceeds in a top-down fashion, progressively adding design detail in each phase. A proprietary software tool combined with VHDL modeling allow test information to automatically migrate through each phase. This allows system implementation to be verified against the original top-level specification. This method of automated test procedure generation provides significant insight into system operation.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129773524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243904
M. Didic
For the validation of the computer-integrated manufacturing (CIM) open system architecture (CIM-OSA), a demonstrator called McCIM has been developed. The first steps in linking the CIM-OSA modeling framework and its integrating infrastructure (IIS) are described. Models of CIM applications are executed by the IIS to run a rapid prototype of online model-based flexible manufacturing. The manufacturing automation protocol (MAP) and the related manufacturing message specification (MMS) are used for the communication between network nodes and various components inside the network nodes.<>
{"title":"Rapid prototyping for MAP/MMS based CIM-OSA environments","authors":"M. Didic","doi":"10.1109/IWRSP.1992.243904","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243904","url":null,"abstract":"For the validation of the computer-integrated manufacturing (CIM) open system architecture (CIM-OSA), a demonstrator called McCIM has been developed. The first steps in linking the CIM-OSA modeling framework and its integrating infrastructure (IIS) are described. Models of CIM applications are executed by the IIS to run a rapid prototype of online model-based flexible manufacturing. The manufacturing automation protocol (MAP) and the related manufacturing message specification (MMS) are used for the communication between network nodes and various components inside the network nodes.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117291073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243899
R. MacDonald, S. Srinivasan, Ronald D. Williams, J. Aylor
There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.<>
需要一种设计方法，允许在不同层次的抽象和解释上表示和模拟设计。提出的单路径设计方法是解决这一问题的可能方法。该方法的基本概念是使用一种仿真语言，即VHSIC硬件描述语言(VHDL, Version 1076)进行所有阶段的设计。VHDL框架允许对模型进行迭代的逐步细化。可以将性能(未解释的)模型细化为寄存器传输级别(RTL)描述，而无需更改建模环境或完全重写模型。作为一个例子，单路径设计方法的性能建模阶段应用于WM机器，这是一个超标量计算机体系结构。
{"title":"A novel VHDL-based computer architecture design methodology","authors":"R. MacDonald, S. Srinivasan, Ronald D. Williams, J. Aylor","doi":"10.1109/IWRSP.1992.243899","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243899","url":null,"abstract":"There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243919
R. Lauwereins, M. Engels, J. Peperstraete
The second version of the graphical programming environment (GRAPE) is described. It is intended as a tool for the rapid prototyping of digital signal processing (DSP) application-specific integrated circuits (ASICs) on a multiprocessor. GRAPE-II fully supports multirate and asynchronous DSP applications and heterogeneous target multiprocessors. The extensions that are required to the programming model and the intermediate specification language to support multirate and asynchronous operation are described. The programming model is clarified by an example. The global structure of GRAPE-II is presented. The status of the project is indicated.<>
{"title":"GRAPE-II: a tool for the rapid prototyping of multi-rate asynchronous DSP applications on heterogeneous multiprocessors","authors":"R. Lauwereins, M. Engels, J. Peperstraete","doi":"10.1109/IWRSP.1992.243919","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243919","url":null,"abstract":"The second version of the graphical programming environment (GRAPE) is described. It is intended as a tool for the rapid prototyping of digital signal processing (DSP) application-specific integrated circuits (ASICs) on a multiprocessor. GRAPE-II fully supports multirate and asynchronous DSP applications and heterogeneous target multiprocessors. The extensions that are required to the programming model and the intermediate specification language to support multirate and asynchronous operation are described. The programming model is clarified by an example. The global structure of GRAPE-II is presented. The status of the project is indicated.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129631636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243914
O. Tanir, V. Agarwal, P. Bhatt
A framework for system level synthesis is presented, and a suitable language, DSL, for capturing design specifications and generating control graphs amiable to synthesis is proposed. The three stages in the synthesis process-design specification, intermediate representation, and synthesis-are examined in detail. A rough version of the language is used to model a simple system.<>
{"title":"A system level synthesis framework for computer architectures","authors":"O. Tanir, V. Agarwal, P. Bhatt","doi":"10.1109/IWRSP.1992.243914","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243914","url":null,"abstract":"A framework for system level synthesis is presented, and a suitable language, DSL, for capturing design specifications and generating control graphs amiable to synthesis is proposed. The three stages in the synthesis process-design specification, intermediate representation, and synthesis-are examined in detail. A rough version of the language is used to model a simple system.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116120353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-06-23DOI: 10.1109/IWRSP.1992.243900
J. Beetem
Graphical visualization of algorithm behavior can be a powerful technique for assessing the effectiveness of different algorithms and heuristics, provided that the graphical user interface (GUI) can be prototyped and modified quickly. Visualization was used to prototype a placement and routing package for the MITRE digital transform machine (DTM), a reconfigurable logic array. Use of the galaxy, programming language and environment greatly simplified GUI construction, allowing the prototyper to concentrate on placement and routing algorithms instead of the details of conventional GUI programming.<>
{"title":"Visualizing optimization algorithms via rapid prototyping of graphical user interfaces","authors":"J. Beetem","doi":"10.1109/IWRSP.1992.243900","DOIUrl":"https://doi.org/10.1109/IWRSP.1992.243900","url":null,"abstract":"Graphical visualization of algorithm behavior can be a powerful technique for assessing the effectiveness of different algorithms and heuristics, provided that the graphical user interface (GUI) can be prototyped and modified quickly. Visualization was used to prototype a placement and routing package for the MITRE digital transform machine (DTM), a reconfigurable logic array. Use of the galaxy, programming language and environment greatly simplified GUI construction, allowing the prototyper to concentrate on placement and routing algorithms instead of the details of conventional GUI programming.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131696603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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