Pub Date : 2023-03-09DOI: 10.1109/CAE56623.2023.10086975
J. I. Morales, F. Chierchie, P. Mandolesi, E. Paolini
Two all-digital transmitter architectures with distortion-free pulse width modulation are presented in this work. The modulation achieves a clean spectrum free of spurious even when a low number of quantization levels are used, allowing their implementation using clock-based schemes on general purposes FPGAs. The influence of the oversampling on the performance is evaluated in terms of the adjacent channel power ratio (ACPR) for different values of time resolution. Values of ACPR1 and ACPR2 better than −45 dBc and −42 dBc, respectively, are achieved using only 11 resolution time steps in the binary signal and an oversampling ratio between the carrier and baseband signal frequencies of 64. The architectures are verified by FPGA implementations using 64-QAM modulated signal and carrier frequencies in two ISM bands (13.56 MHz and 40.68 MHz), utilizing less than 1% of the available resources.
{"title":"An FPGA RF PWM Modulator for ISM Bands","authors":"J. I. Morales, F. Chierchie, P. Mandolesi, E. Paolini","doi":"10.1109/CAE56623.2023.10086975","DOIUrl":"https://doi.org/10.1109/CAE56623.2023.10086975","url":null,"abstract":"Two all-digital transmitter architectures with distortion-free pulse width modulation are presented in this work. The modulation achieves a clean spectrum free of spurious even when a low number of quantization levels are used, allowing their implementation using clock-based schemes on general purposes FPGAs. The influence of the oversampling on the performance is evaluated in terms of the adjacent channel power ratio (ACPR) for different values of time resolution. Values of ACPR1 and ACPR2 better than −45 dBc and −42 dBc, respectively, are achieved using only 11 resolution time steps in the binary signal and an oversampling ratio between the carrier and baseband signal frequencies of 64. The architectures are verified by FPGA implementations using 64-QAM modulated signal and carrier frequencies in two ISM bands (13.56 MHz and 40.68 MHz), utilizing less than 1% of the available resources.","PeriodicalId":212534,"journal":{"name":"2023 Argentine Conference on Electronics (CAE)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121613282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-09DOI: 10.1109/CAE56623.2023.10087013
Jorge Marin, J. Gak, A. Cortés, Nicolás Calarco, A. Oliva, E. Lindstrom, M. Miguez, Alfredo Falcon, Niria Osterman, C. Rojas
In this work, the design, simulation and implementation of a DC-DC buck converter based on the Three-level Flying Capacitor Converter architecture for space applications, namely CubeSat systems, using the Skywater 130nm CMOS technology is presented. The power circuits are fully integrated on-chip, including the power MOSFETs and the gate drivers, to obtain an efficient and compact implementation. This versatile power electronics building block, is also a contribution to the open source IC design community. Additionally, tests structures for the flying capacitor and the output filter inductors are included to characterize the technology passive. The active area of the dual-core circuit (including power switches and drivers) occupies less than 1mm2 of silicon in this process. Simulated results shows a peak efficiency of 87% at 140mA load current for the single core converter, and a peak efficiency of 93.3% at 555mA load current for the dual-core converter, at 1MHz switching frequency. It also shows a 85% peak efficiency for full on-chip flying capacitor single-core implementation at 10MHz operation.
{"title":"Integrated Three-Level Flying Capacitor DC-DC Buck Converter for CubeSat Applications","authors":"Jorge Marin, J. Gak, A. Cortés, Nicolás Calarco, A. Oliva, E. Lindstrom, M. Miguez, Alfredo Falcon, Niria Osterman, C. Rojas","doi":"10.1109/CAE56623.2023.10087013","DOIUrl":"https://doi.org/10.1109/CAE56623.2023.10087013","url":null,"abstract":"In this work, the design, simulation and implementation of a DC-DC buck converter based on the Three-level Flying Capacitor Converter architecture for space applications, namely CubeSat systems, using the Skywater 130nm CMOS technology is presented. The power circuits are fully integrated on-chip, including the power MOSFETs and the gate drivers, to obtain an efficient and compact implementation. This versatile power electronics building block, is also a contribution to the open source IC design community. Additionally, tests structures for the flying capacitor and the output filter inductors are included to characterize the technology passive. The active area of the dual-core circuit (including power switches and drivers) occupies less than 1mm2 of silicon in this process. Simulated results shows a peak efficiency of 87% at 140mA load current for the single core converter, and a peak efficiency of 93.3% at 555mA load current for the dual-core converter, at 1MHz switching frequency. It also shows a 85% peak efficiency for full on-chip flying capacitor single-core implementation at 10MHz operation.","PeriodicalId":212534,"journal":{"name":"2023 Argentine Conference on Electronics (CAE)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122647282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-09DOI: 10.1109/CAE56623.2023.10087014
Italo Bruni, F. Olivera, A. Petraglia
This paper proposes a CMOS current reference circuit that avoids the use of huge area resistors. In order to achieve an independent-of-absolute-temperature (IOAT) current, proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages are respectively applied to the drain and gate terminals of a n-MOS pseudo-resistor. The circuit was carried out using a 180 nm CMOS process. Extensive post-layout simulation results in Spectre show that the proposed topology presents a current consumption of 6.30 nA (typical), a temperature coefficient (TC) of 219 ppm/°C in a range from −40 to 120 °C, and a line regulation (LR) of 12.08 %. The proposed current reference occupies a silicon area of 0.0018 mm2.
{"title":"Nano-Ampere Area-Efficient Current Reference Based on Temperature-Controlled Pseudo-Resistor","authors":"Italo Bruni, F. Olivera, A. Petraglia","doi":"10.1109/CAE56623.2023.10087014","DOIUrl":"https://doi.org/10.1109/CAE56623.2023.10087014","url":null,"abstract":"This paper proposes a CMOS current reference circuit that avoids the use of huge area resistors. In order to achieve an independent-of-absolute-temperature (IOAT) current, proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages are respectively applied to the drain and gate terminals of a n-MOS pseudo-resistor. The circuit was carried out using a 180 nm CMOS process. Extensive post-layout simulation results in Spectre show that the proposed topology presents a current consumption of 6.30 nA (typical), a temperature coefficient (TC) of 219 ppm/°C in a range from −40 to 120 °C, and a line regulation (LR) of 12.08 %. The proposed current reference occupies a silicon area of 0.0018 mm2.","PeriodicalId":212534,"journal":{"name":"2023 Argentine Conference on Electronics (CAE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132673256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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