This paper describes the architecture and the current implementation of the hardware unification unit (HUU). The HUU performs the literal unification operation in Prolog processing. It is designed as a coprocessor to a host system that handles other operations of Prolog processing such as bookkeeping and sequencing. After the host system provides input values to the HUU and activates it, the HUU works independently from the host system; when it finishes its operation it reports the result to the host system. The HUU contains local memory that stores the variable binding information. The microinstructions and a sample microprogram of the HUU are described. Performance measures obtained from the HUU simulator are presented and discussed.
{"title":"The architecture of the hardware unification unit and an implementation","authors":"N. Woo","doi":"10.1145/18927.18915","DOIUrl":"https://doi.org/10.1145/18927.18915","url":null,"abstract":"This paper describes the architecture and the current implementation of the hardware unification unit (HUU). The HUU performs the literal unification operation in Prolog processing. It is designed as a coprocessor to a host system that handles other operations of Prolog processing such as bookkeeping and sequencing. After the host system provides input values to the HUU and activates it, the HUU works independently from the host system; when it finishes its operation it reports the result to the host system. The HUU contains local memory that stores the variable binding information. The microinstructions and a sample microprogram of the HUU are described. Performance measures obtained from the HUU simulator are presented and discussed.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124059768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
STEP Development Tools (SDT) is a general-purpose microprogram development system. The METASTEP language system is composed of four tools of the SDT needed to write microprograms: a Definition Processor, a Retargetable Assembler, a Retargetable Cross-Assembler, and a Relocatable Linker. These tools are of commercial quality, providing complete languages, quality diagnostics, full interface to other support tools, and high performance. The language system supports microcode debug by providing complete run-time information and by interacting directly with other debug tools provided in SDT.
{"title":"STEP development tools: METASTEP language system","authors":"D. Wilburn, Stephen Schleimer","doi":"10.1145/18927.18922","DOIUrl":"https://doi.org/10.1145/18927.18922","url":null,"abstract":"STEP Development Tools (SDT) is a general-purpose microprogram development system. The METASTEP language system is composed of four tools of the SDT needed to write microprograms: a Definition Processor, a Retargetable Assembler, a Retargetable Cross-Assembler, and a Relocatable Linker.\u0000These tools are of commercial quality, providing complete languages, quality diagnostics, full interface to other support tools, and high performance. The language system supports microcode debug by providing complete run-time information and by interacting directly with other debug tools provided in SDT.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123492748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a microcode-evaluation methodology. The supporting test tools were developed by the IBM General Products Division in Tucson, Arizona, to allow effective and comprehensive evaluations of microcode systems. The methodology has been used successfully by the Tucson Test Laboratory (TTL) during the past several years. The evaluation methodology is characterized by an integrated application of static and dynamic analysis techniques. These two modes of analysis are complementary and they allow a level of automation that can significantly enhance the productivity of a testing organization through the systematic application of automated testing techniques. The methodology also establishes a discipline for the microcode-testing process that promotes a formal program of defect removal. Of course, improving the process of removing defects produces a corresponding enhancement in product quality.
{"title":"A practical approach to the evaluation of microcode systems","authors":"R. Skibbe","doi":"10.1145/18927.18911","DOIUrl":"https://doi.org/10.1145/18927.18911","url":null,"abstract":"This paper describes a microcode-evaluation methodology. The supporting test tools were developed by the IBM General Products Division in Tucson, Arizona, to allow effective and comprehensive evaluations of microcode systems. The methodology has been used successfully by the Tucson Test Laboratory (TTL) during the past several years.\u0000The evaluation methodology is characterized by an integrated application of static and dynamic analysis techniques. These two modes of analysis are complementary and they allow a level of automation that can significantly enhance the productivity of a testing organization through the systematic application of automated testing techniques. The methodology also establishes a discipline for the microcode-testing process that promotes a formal program of defect removal. Of course, improving the process of removing defects produces a corresponding enhancement in product quality.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130272110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper reports on the control store cost minimization using an approach related to the bit reduction method. A methodology is presented for finding the microinstruction format which provides a minimum joint cost of the control store and microinstruction decoder circuitry for a given set of microprograms. The optimization criterion measures the area taken by the control store and decoders in a large scale integrated circuit. The methodology is based on the concepts of codable microoperation classes and microoperation class distributivity introduced in the paper. The codable classes are those that provide the length reduction of the microinstruction field used for binary encoding microoperation combinations, compared to the single bit/microoperation encoding method. Microoperation class properties and basic types of fields assignments in microinstruction word formats for codable class approach are also discussed.
{"title":"A customized control store design in microprogrammed control units","authors":"M. Tudruj","doi":"10.1145/18927.18926","DOIUrl":"https://doi.org/10.1145/18927.18926","url":null,"abstract":"The paper reports on the control store cost minimization using an approach related to the bit reduction method. A methodology is presented for finding the microinstruction format which provides a minimum joint cost of the control store and microinstruction decoder circuitry for a given set of microprograms. The optimization criterion measures the area taken by the control store and decoders in a large scale integrated circuit. The methodology is based on the concepts of codable microoperation classes and microoperation class distributivity introduced in the paper. The codable classes are those that provide the length reduction of the microinstruction field used for binary encoding microoperation combinations, compared to the single bit/microoperation encoding method. Microoperation class properties and basic types of fields assignments in microinstruction word formats for codable class approach are also discussed.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124536522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale for its selection, and describes the data path and flow of instructions through the microengine.
{"title":"HPS, a new microarchitecture: rationale and introduction","authors":"Y. Patt, Wen-mei W. Hwu, M. Shebanow","doi":"10.1145/18927.18916","DOIUrl":"https://doi.org/10.1145/18927.18916","url":null,"abstract":"HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale for its selection, and describes the data path and flow of instructions through the microengine.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127105157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a hierarchical firmware design method. It allows to structure the design of a microprogrammed (level of a) computer architecture into independently verifiable modules. To specify the behaviour of the system we use the axiomatic architecture description language AADL. We illustrate the design and specification style using an emulation example.
{"title":"Design and specification of microprogrammed computer architectures","authors":"W. Damm","doi":"10.1145/18927.18907","DOIUrl":"https://doi.org/10.1145/18927.18907","url":null,"abstract":"This paper presents a hierarchical firmware design method. It allows to structure the design of a microprogrammed (level of a) computer architecture into independently verifiable modules. To specify the behaviour of the system we use the axiomatic architecture description language AADL. We illustrate the design and specification style using an emulation example.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127523790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current digital logic simulators running on engineering workstations lack capacity and speed. This paper discusses a hardware accelerator for a workstation simulator which addresses these problems. The accelerator runs 100x faster than its software counterpart and can simulate up to 1 million gates. The accelerator has been built and is being sold commercially. The architecture of the accelerator is similar to that of a classical dataflow machine. We describe the architecture of the machine and illustrate how it would simulate a simple circuit. We then briefly discuss the relationship between event driven simulation and dataflow.
{"title":"Hardware acceleration of logic simulation using a data flow microarchitecture","authors":"G. Catlin, Bill Paseman","doi":"10.1145/18927.18918","DOIUrl":"https://doi.org/10.1145/18927.18918","url":null,"abstract":"Current digital logic simulators running on engineering workstations lack capacity and speed. This paper discusses a hardware accelerator for a workstation simulator which addresses these problems. The accelerator runs 100x faster than its software counterpart and can simulate up to 1 million gates. The accelerator has been built and is being sold commercially. The architecture of the accelerator is similar to that of a classical dataflow machine. We describe the architecture of the machine and illustrate how it would simulate a simple circuit. We then briefly discuss the relationship between event driven simulation and dataflow.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127847619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We apply the verification methodology underlying the S*-System[12], [13] to the verification of a hierarchically structured design [16] of an emulation of the instruction-set of a commercially available computer on a commercially available micro-architecture. Based on this case-study, we discuss some aspects of the relation between verification and generation of microcode.
{"title":"Verification of microprogrammed computer architectures in the S*-system: a case study","authors":"W. Damm, Gert Döhmen","doi":"10.1145/18927.18913","DOIUrl":"https://doi.org/10.1145/18927.18913","url":null,"abstract":"We apply the verification methodology underlying the S*-System[12], [13] to the verification of a hierarchically structured design [16] of an emulation of the instruction-set of a commercially available computer on a commercially available micro-architecture. Based on this case-study, we discuss some aspects of the relation between verification and generation of microcode.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122980525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. Unfortunately, programming at the machine-instruction level is both tedious and error-prone. A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures that the resulting code has the same semantics as the original program, generates code where speed is not critical, and performs bookkeeping tasks. We are in the process of implementing a prototype of such a system. This paper describes the system being developed and discusses some of the key design issues.
{"title":"The design of an interactive compiler for optimizing microprograms","authors":"S. Vegdahl","doi":"10.1145/18927.18919","DOIUrl":"https://doi.org/10.1145/18927.18919","url":null,"abstract":"Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. Unfortunately, programming at the machine-instruction level is both tedious and error-prone. A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures that the resulting code has the same semantics as the original program, generates code where speed is not critical, and performs bookkeeping tasks. We are in the process of implementing a prototype of such a system. This paper describes the system being developed and discusses some of the key design issues.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117166089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper is concerned with efficient implementation of evolved modular and structured microprogramming. A microprogrammable architecture is presented that permits designing hierarchical complicated modular microprograms at two distinct levels: the global control and the data processing level. The architecture is based on two cooperating microprogram control units that separately store and perform control and executive microinstructions and microcode modules. The control organization of an implementing computer is presented which assures the quasi time-transparency of modular control in microprograms during the microprogram execution. This is achieved by parallel functioning of constituent control units, that permits preparing in advance addresses of executive modules referenced by control microinstructions. The efficient implementation of control statements of high level languages and microprogramming at the assembler language level for the proposed architecture are also discussed in the paper.
{"title":"A microprogrammable architecture with quasi time-transparent structured control","authors":"M. Tudruj, R. Gajda","doi":"10.1145/18927.18909","DOIUrl":"https://doi.org/10.1145/18927.18909","url":null,"abstract":"The paper is concerned with efficient implementation of evolved modular and structured microprogramming. A microprogrammable architecture is presented that permits designing hierarchical complicated modular microprograms at two distinct levels: the global control and the data processing level. The architecture is based on two cooperating microprogram control units that separately store and perform control and executive microinstructions and microcode modules. The control organization of an implementing computer is presented which assures the quasi time-transparency of modular control in microprograms during the microprogram execution. This is achieved by parallel functioning of constituent control units, that permits preparing in advance addresses of executive modules referenced by control microinstructions. The efficient implementation of control statements of high level languages and microprogramming at the assembler language level for the proposed architecture are also discussed in the paper.","PeriodicalId":221754,"journal":{"name":"MICRO 18","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133642749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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