Máire O’Neill, E. O'Sullivan, Gavin McWilliams, Markku-Juhani O. Saarinen, C. Moore, A. Khalid, James Howe, Rafaël del Pino, Michel Abdalla, F. Regazzoni, Felipe Valencia, T. Güneysu, Tobias Oder, A. Waller, Glyn Jones, Anthony Barnett, Robert Griffin, A. Byrne, Bassem Ammar, David Lund
Funded under the European Union's Horizon 2020 research and innovation programme, SAFEcrypto will provide a new generation of practical, robust and physically secure post-quantum cryptographic solutions that ensure long-term security for future ICT systems, services and applications. The project will focus on the remarkably versatile field of Lattice-based cryptography as the source of computational hardness, and will deliver optimised public key security primitives for digital signatures and authentication, as well identity based encryption (IBE) and attribute based encryption (ABE). This will involve algorithmic and design optimisations, and implementations of lattice-based cryptographic schemes addressing cost, energy consumption, performance and physical robustness. As the National Institute of Standards and Technology (NIST) prepares for the transition to a post-quantum cryptographic suite B, urging organisations that build systems and infrastructures that require long-term security to consider this transition in architectural designs; the SAFEcrypto project will provide Proof-of-concept demonstrators of schemes for three practical real-world case studies with long-term security requirements, in the application areas of satellite communications, network security and cloud. The goal is to affirm Lattice-based cryptography as an effective replacement for traditional number-theoretic public-key cryptography, by demonstrating that it can address the needs of resource-constrained embedded applications, such as mobile and battery-operated devices, and of real-time high performance applications for cloud and network management infrastructures.
{"title":"Secure architectures of future emerging cryptography SAFEcrypto","authors":"Máire O’Neill, E. O'Sullivan, Gavin McWilliams, Markku-Juhani O. Saarinen, C. Moore, A. Khalid, James Howe, Rafaël del Pino, Michel Abdalla, F. Regazzoni, Felipe Valencia, T. Güneysu, Tobias Oder, A. Waller, Glyn Jones, Anthony Barnett, Robert Griffin, A. Byrne, Bassem Ammar, David Lund","doi":"10.1145/2903150.2907756","DOIUrl":"https://doi.org/10.1145/2903150.2907756","url":null,"abstract":"Funded under the European Union's Horizon 2020 research and innovation programme, SAFEcrypto will provide a new generation of practical, robust and physically secure post-quantum cryptographic solutions that ensure long-term security for future ICT systems, services and applications. The project will focus on the remarkably versatile field of Lattice-based cryptography as the source of computational hardness, and will deliver optimised public key security primitives for digital signatures and authentication, as well identity based encryption (IBE) and attribute based encryption (ABE). This will involve algorithmic and design optimisations, and implementations of lattice-based cryptographic schemes addressing cost, energy consumption, performance and physical robustness. As the National Institute of Standards and Technology (NIST) prepares for the transition to a post-quantum cryptographic suite B, urging organisations that build systems and infrastructures that require long-term security to consider this transition in architectural designs; the SAFEcrypto project will provide Proof-of-concept demonstrators of schemes for three practical real-world case studies with long-term security requirements, in the application areas of satellite communications, network security and cloud. The goal is to affirm Lattice-based cryptography as an effective replacement for traditional number-theoretic public-key cryptography, by demonstrating that it can address the needs of resource-constrained embedded applications, such as mobile and battery-operated devices, and of real-time high performance applications for cloud and network management infrastructures.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129046522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sequential pattern mining (SPM) is a widely used data mining technique for discovering common sequences of events in large databases. When compared with the simple set mining problem and string mining problem, the hierarchical structure of sequential pattern mining (due to the need to consider frequent subsets within each itemset, as well as order among itemsets) and the resulting large permutation space makes SPM extremely expensive on conventional processor architectures. We propose a hardware-accelerated solution of the SPM using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs). The Generalized Sequential Pattern (GSP) algorithm for SPM searching exposes massive parallelism, and is therefore well-suited for AP acceleration. We implement the multi-pass pruning strategy of the GSP via the AP's fast reconfigurability. A generalized automaton structure is proposed by flattening sequential patterns to simple strings to reduce compilation time and to minimize overhead of reconfiguration. Up to 90X and 29X speedups are achieved by the AP-accelerated GSP on six real-world datasets, when compared with the optimized multicore CPU and GPU GSP implementations, respectively. The proposed CPU-AP solution also outperforms the state-of-the-art PrefixSpan and SPADE algorithms on multicore CPU by up to 452X and 49X speedups. The AP advantage grows further with larger datasets.
{"title":"Sequential pattern mining with the Micron automata processor","authors":"Ke Wang, Elaheh Sadredini, K. Skadron","doi":"10.1145/2903150.2903172","DOIUrl":"https://doi.org/10.1145/2903150.2903172","url":null,"abstract":"Sequential pattern mining (SPM) is a widely used data mining technique for discovering common sequences of events in large databases. When compared with the simple set mining problem and string mining problem, the hierarchical structure of sequential pattern mining (due to the need to consider frequent subsets within each itemset, as well as order among itemsets) and the resulting large permutation space makes SPM extremely expensive on conventional processor architectures. We propose a hardware-accelerated solution of the SPM using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs). The Generalized Sequential Pattern (GSP) algorithm for SPM searching exposes massive parallelism, and is therefore well-suited for AP acceleration. We implement the multi-pass pruning strategy of the GSP via the AP's fast reconfigurability. A generalized automaton structure is proposed by flattening sequential patterns to simple strings to reduce compilation time and to minimize overhead of reconfiguration. Up to 90X and 29X speedups are achieved by the AP-accelerated GSP on six real-world datasets, when compared with the optimized multicore CPU and GPU GSP implementations, respectively. The proposed CPU-AP solution also outperforms the state-of-the-art PrefixSpan and SPADE algorithms on multicore CPU by up to 452X and 49X speedups. The AP advantage grows further with larger datasets.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124457462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Alpár, L. Batina, L. Batten, Veelasha Moonsamy, A. Krasnova, Antoine Guellier, Iynkaran Natgunanathan
The Internet of Things (IoT) is a ubiquitous system that incorporates not only the current Internet of computers, but also smart objects and sensors. IoT technologies often rely on centralised architectures that follow the current business models. This makes efficient data collection and processing possible, which can be beneficial from a business perspective, but has many ramifications for users privacy. As communication within the IoT happens among many devices from various contexts, they need to authenticate each other to know that they talk to the intended party. Authentication, typically including identification, is the proof of identity information. However, transactions linked to the same identifier are traceable, and ultimately make people also traceable, hence their privacy is threatened. We propose a framework to counter this problem. We argue that applying attribute-based (AB) authentication in the context of IoT empowers users to maintain control over what data their devices disclose. At the same time AB authentication provides the possibility of data minimisation and unlinkability of user transactions. Therefore, this approach improves substantially user privacy in the IoT.
{"title":"New directions in IoT privacy using attribute-based authentication","authors":"G. Alpár, L. Batina, L. Batten, Veelasha Moonsamy, A. Krasnova, Antoine Guellier, Iynkaran Natgunanathan","doi":"10.1145/2903150.2911710","DOIUrl":"https://doi.org/10.1145/2903150.2911710","url":null,"abstract":"The Internet of Things (IoT) is a ubiquitous system that incorporates not only the current Internet of computers, but also smart objects and sensors. IoT technologies often rely on centralised architectures that follow the current business models. This makes efficient data collection and processing possible, which can be beneficial from a business perspective, but has many ramifications for users privacy. As communication within the IoT happens among many devices from various contexts, they need to authenticate each other to know that they talk to the intended party. Authentication, typically including identification, is the proof of identity information. However, transactions linked to the same identifier are traceable, and ultimately make people also traceable, hence their privacy is threatened. We propose a framework to counter this problem. We argue that applying attribute-based (AB) authentication in the context of IoT empowers users to maintain control over what data their devices disclose. At the same time AB authentication provides the possibility of data minimisation and unlinkability of user transactions. Therefore, this approach improves substantially user privacy in the IoT.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122580194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daniele Bortolotti, Andrea Bartolini, L. Benini, V. R. Pamula, N. V. Helleputte, C. Hoof, M. Verhelst, T. Gemmeke, Rubén Braojos Lopez, G. Ansaloni, David Atienza Alonso, P. Vandergheynst
Emerging and future HealthCare policies are fueling up an application-driven shift toward long-term monitoring of biosignals by means of embedded ultra-low power Wireless Body Sensor Networks (WBSNs). In order to break out, these applications needed the emergence of new technologies to allow the development of extremely power-efficient bio-sensing nodes. The PHIDIAS project aims at unlocking the development of ultra-low power bio-sensing WBSNs by tackling multiple and interlocking technological breakthroughs: (i) the development of new signal processing models and methods based on the recently proposed Compressive Sampling paradigm, which allows the design of energy-minimal computational architectures and analog front-ends, (ii) the efficient hardware implementation of components, both analog and digital, building upon an innovative ultra-low-power signal processing front-end, (iii) the evaluation of the global power reduction using a system wide integration of hardware and software components focused on compressed-sensing-based bio-signals analysis. PHIDIAS brought together a mixed consortium of academic and industrial research partners representing pan-European excellence in different fields impacting the energy-aware optimization of WBSNs, including experts in signal processing and digital/analog IC design. In this way, PHIDIAS pioneered a unique holistic approach, ensuring that key breakthroughs worked out in a cooperative way toward the global objective of the project.
{"title":"PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms","authors":"Daniele Bortolotti, Andrea Bartolini, L. Benini, V. R. Pamula, N. V. Helleputte, C. Hoof, M. Verhelst, T. Gemmeke, Rubén Braojos Lopez, G. Ansaloni, David Atienza Alonso, P. Vandergheynst","doi":"10.1145/2903150.2903469","DOIUrl":"https://doi.org/10.1145/2903150.2903469","url":null,"abstract":"Emerging and future HealthCare policies are fueling up an application-driven shift toward long-term monitoring of biosignals by means of embedded ultra-low power Wireless Body Sensor Networks (WBSNs). In order to break out, these applications needed the emergence of new technologies to allow the development of extremely power-efficient bio-sensing nodes. The PHIDIAS project aims at unlocking the development of ultra-low power bio-sensing WBSNs by tackling multiple and interlocking technological breakthroughs: (i) the development of new signal processing models and methods based on the recently proposed Compressive Sampling paradigm, which allows the design of energy-minimal computational architectures and analog front-ends, (ii) the efficient hardware implementation of components, both analog and digital, building upon an innovative ultra-low-power signal processing front-end, (iii) the evaluation of the global power reduction using a system wide integration of hardware and software components focused on compressed-sensing-based bio-signals analysis. PHIDIAS brought together a mixed consortium of academic and industrial research partners representing pan-European excellence in different fields impacting the energy-aware optimization of WBSNs, including experts in signal processing and digital/analog IC design. In this way, PHIDIAS pioneered a unique holistic approach, ensuring that key breakthroughs worked out in a cooperative way toward the global objective of the project.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123149120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhuang Wang, Ke Liu, Long Li, Weiyi Chen, Mingyu Chen, Lixin Zhang
Wavelength division multiplexing (WDM) optical networks are becoming more attractive due to their unprecedented high bandwidth provisions and reliability over data transmission among nodes. Therefore, it is not uncommon for enterprises to build a datacenter with over thousands of nodes using WDM optical networks. To reach the high speed over optical links, all-optical, i.e., single hop, networks are desirable as there is no overhead on conversions to and from the electronic form compared to multi-hop networks. However, given the number of nodes required, few previous works suggested a topology, e.g., torus, to support all-to-all routing with the minimum number of wavelengths over all-optical networks. In this paper, we address this challenge from a different angle. Specifically, it is possible to build different torus topologies by altering the number of nodes in every dimension, but we first show that the minimum number of wavelengths to satisfy the all-to-all routing over torus is N/3, and prove that the necessary and sufficient condition to achieve it is the sides of all dimensions are 3; thus the resultant topology is an n-dimensional hypersquare torus network; then we develop a wavelength assignment to achieve the all-to-all routing over the corresponding n-dimensional hypersquare torus; finally, we consider the fail-over problem in our proposed topology and derive the minimum number of backup wavelengths to mitigate the affected lightpaths thus maintain the gossiping.
{"title":"A novel approach for all-to-all routing in all-optical hypersquare torus network","authors":"Zhuang Wang, Ke Liu, Long Li, Weiyi Chen, Mingyu Chen, Lixin Zhang","doi":"10.1145/2903150.2903173","DOIUrl":"https://doi.org/10.1145/2903150.2903173","url":null,"abstract":"Wavelength division multiplexing (WDM) optical networks are becoming more attractive due to their unprecedented high bandwidth provisions and reliability over data transmission among nodes. Therefore, it is not uncommon for enterprises to build a datacenter with over thousands of nodes using WDM optical networks. To reach the high speed over optical links, all-optical, i.e., single hop, networks are desirable as there is no overhead on conversions to and from the electronic form compared to multi-hop networks. However, given the number of nodes required, few previous works suggested a topology, e.g., torus, to support all-to-all routing with the minimum number of wavelengths over all-optical networks. In this paper, we address this challenge from a different angle. Specifically, it is possible to build different torus topologies by altering the number of nodes in every dimension, but we first show that the minimum number of wavelengths to satisfy the all-to-all routing over torus is N/3, and prove that the necessary and sufficient condition to achieve it is the sides of all dimensions are 3; thus the resultant topology is an n-dimensional hypersquare torus network; then we develop a wavelength assignment to achieve the all-to-all routing over the corresponding n-dimensional hypersquare torus; finally, we consider the fail-over problem in our proposed topology and derive the minimum number of backup wavelengths to mitigate the affected lightpaths thus maintain the gossiping.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121382632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Soft error rates in processors have been increasing with decreasing feature size and larger chips. Software-only solutions have been proposed to deal with this problem, for instance via instruction duplication. However, this leads to significant overheads in performance and energy. This paper proposes a novel approach to instruction duplication, which exploits the redundancy within SIMD instructions. The proposed solution is implemented in the LLVM compiler. Execution of a set of compiled C/C++ benchmarks shows that the SIMD based instruction duplication introduces a 32% performance and an 25% energy overheads, respectively, over the baseline. The performance and energy overheads of the state-of-the-art scalar instruction duplication approach are, on average, 111% and 114%, repsectively.
{"title":"SIMD-based soft error detection","authors":"Zhi Chen, A. Nicolau, A. Veidenbaum","doi":"10.1145/2903150.2903170","DOIUrl":"https://doi.org/10.1145/2903150.2903170","url":null,"abstract":"Soft error rates in processors have been increasing with decreasing feature size and larger chips. Software-only solutions have been proposed to deal with this problem, for instance via instruction duplication. However, this leads to significant overheads in performance and energy. This paper proposes a novel approach to instruction duplication, which exploits the redundancy within SIMD instructions. The proposed solution is implemented in the LLVM compiler. Execution of a set of compiled C/C++ benchmarks shows that the SIMD based instruction duplication introduces a 32% performance and an 25% energy overheads, respectively, over the baseline. The performance and energy overheads of the state-of-the-art scalar instruction duplication approach are, on average, 111% and 114%, repsectively.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131365942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Palossi, M. Furci, R. Naldi, A. Marongiu, L. Marconi, L. Benini
We propose a shortest trajectory planning algorithm implementation for Unmanned Aerial Vehicles (UAVs) on an embedded GPU. Our goal is the development of a fast, energy-efficient global planner for multi-rotor UAVs supporting human operator during rescue missions. The work is based on OpenCL parallel non-deterministic version of the Dijkstra algorithm to solve the Single Source Shortest Path (SSSP). Our planner is suitable for real-time path re-computation in dynamically varying environments of up to 200 m2. Results demonstrate the efficacy of the approach, showing speedups of up to 74x, saving up to ~ 98% of energy versus the sequential benchmark, while reaching near-optimal path selection, keeping the average path cost error smaller than 1.2%.
{"title":"An energy-efficient parallel algorithm for real-time near-optimal UAV path planning","authors":"D. Palossi, M. Furci, R. Naldi, A. Marongiu, L. Marconi, L. Benini","doi":"10.1145/2903150.2911712","DOIUrl":"https://doi.org/10.1145/2903150.2911712","url":null,"abstract":"We propose a shortest trajectory planning algorithm implementation for Unmanned Aerial Vehicles (UAVs) on an embedded GPU. Our goal is the development of a fast, energy-efficient global planner for multi-rotor UAVs supporting human operator during rescue missions. The work is based on OpenCL parallel non-deterministic version of the Dijkstra algorithm to solve the Single Source Shortest Path (SSSP). Our planner is suitable for real-time path re-computation in dynamically varying environments of up to 200 m2. Results demonstrate the efficacy of the approach, showing speedups of up to 74x, saving up to ~ 98% of energy versus the sequential benchmark, while reaching near-optimal path selection, keeping the average path cost error smaller than 1.2%.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiang Fu, L. Riesebos, L. Lao, C. G. Almudever, F. Sebastiano, R. Versluis, E. Charbon, K. Bertels
In this paper, we present a high level view of the heterogeneous quantum computer architecture as any future quantum computer will consist of both a classical and quantum computing part. The classical part is needed for error correction as well as for the execution of algorithms that contain both classical and quantum logic. We present a complete system stack describing the different layers when building a quantum computer. We also present the control logic and corresponding data path that needs to be implemented when executing quantum instructions and conclude by discussing design choices in the quantum plane.
{"title":"A heterogeneous quantum computer architecture","authors":"Xiang Fu, L. Riesebos, L. Lao, C. G. Almudever, F. Sebastiano, R. Versluis, E. Charbon, K. Bertels","doi":"10.1145/2903150.2906827","DOIUrl":"https://doi.org/10.1145/2903150.2906827","url":null,"abstract":"In this paper, we present a high level view of the heterogeneous quantum computer architecture as any future quantum computer will consist of both a classical and quantum computing part. The classical part is needed for error correction as well as for the execution of algorithms that contain both classical and quantum logic. We present a complete system stack describing the different layers when building a quantum computer. We also present the control logic and corresponding data path that needs to be implemented when executing quantum instructions and conclude by discussing design choices in the quantum plane.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127044201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jin-hua Zha, Linpeng Huang, L. Wu, Shengan Zheng, H. Liu
Non-Volatile Memory (NVM) has evolved to achieve non-volatility and byte-addressability with latency comparable to DRAM. This inspires the development of a new generation of file systems, namely NVM-based in-memory file systems, which include NVM on memory bus and allow in-NVM data to be directly accessed like DRAM. Meanwhile, an important issue, the consistency problem, arises as a new challenge. That is, the direct modification to the in-NVM data can be interrupted by arbitrary crashes in the system, which results in part of the modification being durable and others being lost. Traditional consistency mechanisms assume the existence of DRAM buffering and hence cannot be applied to this hybrid memory architecture. While several consistency methods have been proposed for NVM-based in-memory file systems, most of them have side-effects including unfriendliness to DRAM and penalties on concurrency control, which degrade the system performance. In this paper, we propose a novel mechanism to guarantee the consistency of NVM-based in-memory file systems. We abstract the storage area as a layered structure and employ a lazy-validated snapshot strategy to achieve a high consistency level. Since every consistency method comes with a cost, we introduce several algorithms to efficiently deal with block-sharing and reduce the overhead of consistency mechanism. The experimental results show that our mechanism incurs negligible consistency overhead and outperforms a state-of-the-art snapshot file system by reducing the latency of snapshot taking and removal by 95% and 60% respectively.
{"title":"A consistency mechanism for NVM-Based in-memory file systems","authors":"Jin-hua Zha, Linpeng Huang, L. Wu, Shengan Zheng, H. Liu","doi":"10.1145/2903150.2903160","DOIUrl":"https://doi.org/10.1145/2903150.2903160","url":null,"abstract":"Non-Volatile Memory (NVM) has evolved to achieve non-volatility and byte-addressability with latency comparable to DRAM. This inspires the development of a new generation of file systems, namely NVM-based in-memory file systems, which include NVM on memory bus and allow in-NVM data to be directly accessed like DRAM. Meanwhile, an important issue, the consistency problem, arises as a new challenge. That is, the direct modification to the in-NVM data can be interrupted by arbitrary crashes in the system, which results in part of the modification being durable and others being lost. Traditional consistency mechanisms assume the existence of DRAM buffering and hence cannot be applied to this hybrid memory architecture. While several consistency methods have been proposed for NVM-based in-memory file systems, most of them have side-effects including unfriendliness to DRAM and penalties on concurrency control, which degrade the system performance. In this paper, we propose a novel mechanism to guarantee the consistency of NVM-based in-memory file systems. We abstract the storage area as a layered structure and employ a lazy-validated snapshot strategy to achieve a high consistency level. Since every consistency method comes with a cost, we introduce several algorithms to efficiently deal with block-sharing and reduce the overhead of consistency mechanism. The experimental results show that our mechanism incurs negligible consistency overhead and outperforms a state-of-the-art snapshot file system by reducing the latency of snapshot taking and removal by 95% and 60% respectively.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122435343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing number of cores in embedded devices results in improved performance compared to single-core systems. Further, the unique characteristics of these systems provide numerous opportunities for power management which require models for power estimation. In this work, a statistical approach that models the impact of the individual cores and memory hierarchy on overall power consumed by Chip Multiprocessors is developed using Performance Counters. In particular, we construct a per-core based power model using SPLASH2 benchmarks by leveraging concurrency for multicore systems. Our model is simple and technology independent and as a result executes faster incurring lesser overhead. Evaluation of the model shows a strong correlation between core-level activity and power consumption and that the model predicts power consumption for newer observations with minimal errors. In addition, we discuss a few applications where the model can be utilized towards estimating power consumption.
{"title":"Predictive modeling based power estimation for embedded multicore systems","authors":"S. Sankaran","doi":"10.1145/2903150.2911714","DOIUrl":"https://doi.org/10.1145/2903150.2911714","url":null,"abstract":"The increasing number of cores in embedded devices results in improved performance compared to single-core systems. Further, the unique characteristics of these systems provide numerous opportunities for power management which require models for power estimation. In this work, a statistical approach that models the impact of the individual cores and memory hierarchy on overall power consumed by Chip Multiprocessors is developed using Performance Counters. In particular, we construct a per-core based power model using SPLASH2 benchmarks by leveraging concurrency for multicore systems. Our model is simple and technology independent and as a result executes faster incurring lesser overhead. Evaluation of the model shows a strong correlation between core-level activity and power consumption and that the model predicts power consumption for newer observations with minimal errors. In addition, we discuss a few applications where the model can be utilized towards estimating power consumption.","PeriodicalId":226569,"journal":{"name":"Proceedings of the ACM International Conference on Computing Frontiers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114697700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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