Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495200
Robert I. Davis, A. Wellings
In this paper, we present a new strategy for scheduling tasks with soft deadlines in real-time systems containing periodic, sporadic and adaptive tasks with hard deadlines. In such systems, much of the spare capacity present is due to sporadic and adaptive tasks not arriving at their maximum rate. Offline methods of identifying spare capacity such as the Deferrable Server or Priority Exchange Algorithm are unable to make this spare capacity available as anything other than a background service opportunity for soft tasks. Further, more recent methods such as dynamic Slack Stealing require computationally expensive re-evaluation of the available slack in order to reclaim such spare capacity. By comparison, the Dual Priority approach presented in this paper provides an efficient and effective means of scheduling soft task in this case.
{"title":"Dual priority scheduling","authors":"Robert I. Davis, A. Wellings","doi":"10.1109/REAL.1995.495200","DOIUrl":"https://doi.org/10.1109/REAL.1995.495200","url":null,"abstract":"In this paper, we present a new strategy for scheduling tasks with soft deadlines in real-time systems containing periodic, sporadic and adaptive tasks with hard deadlines. In such systems, much of the spare capacity present is due to sporadic and adaptive tasks not arriving at their maximum rate. Offline methods of identifying spare capacity such as the Deferrable Server or Priority Exchange Algorithm are unable to make this spare capacity available as anything other than a background service opportunity for soft tasks. Further, more recent methods such as dynamic Slack Stealing require computationally expensive re-evaluation of the available slack in order to reclaim such spare capacity. By comparison, the Dual Priority approach presented in this paper provides an efficient and effective means of scheduling soft task in this case.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130008377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495223
J. Sasinowski, J. Strosnider
Multimedia and advanced real-time systems integrate a variety of applications and media types in one environment, many of which have timing properties which are not supported by current window systems running in multitasking environments. This paper discusses several key aspects to designing window systems which support continuous media and other real-time applications. These design considerations were used to construct ARTIFACT, a window system designed to investigate issues in building real-time window systems. Several of the behaviors of a partial implementation of ARTIFACT are described, along with preliminary scheduling models and avenues for further research.
{"title":"ARTIFACT: a platform for evaluating real-time window system designs","authors":"J. Sasinowski, J. Strosnider","doi":"10.1109/REAL.1995.495223","DOIUrl":"https://doi.org/10.1109/REAL.1995.495223","url":null,"abstract":"Multimedia and advanced real-time systems integrate a variety of applications and media types in one environment, many of which have timing properties which are not supported by current window systems running in multitasking environments. This paper discusses several key aspects to designing window systems which support continuous media and other real-time applications. These design considerations were used to construct ARTIFACT, a window system designed to investigate issues in building real-time window systems. Several of the behaviors of a partial implementation of ARTIFACT are described, along with preliminary scheduling models and avenues for further research.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122627999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495216
Jin-Young Choi, Insup Lee, H. Xie
To engineer reliable real-time systems, it is desirable to detect timing anomalies early in the development process. However, there is little work addressing the problem of accurately predicting timing properties of real-time systems before implementations are developed. This paper describes an approach to the specification and schedulability analysis of real-time systems based on the timed process algebra ACSR-VP, which is an extension of algebra of communicating shared resources (ACSR) with value-passing communication and dynamic priorities. Combined with the existing features of ACSR for representing time, synchronization and resource requirements, ACSR-VP is capable of specifying a variety of real-time systems with different scheduling disciplines in a modular fashion. Moreover, we can perform schedulability analysis on real-time systems specified in ACSR-VP automatically by checking for a certain bisimulation relation.
{"title":"The specification and schedulability analysis of real-time systems using ACSR","authors":"Jin-Young Choi, Insup Lee, H. Xie","doi":"10.1109/REAL.1995.495216","DOIUrl":"https://doi.org/10.1109/REAL.1995.495216","url":null,"abstract":"To engineer reliable real-time systems, it is desirable to detect timing anomalies early in the development process. However, there is little work addressing the problem of accurately predicting timing properties of real-time systems before implementations are developed. This paper describes an approach to the specification and schedulability analysis of real-time systems based on the timed process algebra ACSR-VP, which is an extension of algebra of communicating shared resources (ACSR) with value-passing communication and dynamic priorities. Combined with the existing features of ACSR for representing time, synchronization and resource requirements, ACSR-VP is capable of specifying a variety of real-time systems with different scheduling disciplines in a modular fashion. Moreover, we can perform schedulability analysis on real-time systems specified in ACSR-VP automatically by checking for a certain bisimulation relation.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"11 s3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495212
C. Han, J. Hou, K. Shin
DQDB is a MAC protocol jointly adopted by IEEE and ANSI as the candidate protocol for MANs, and has been studied by many researchers. Previously, we laid a formal basis for guaranteeing the timely delivery of isochronous (real-time) messages with hard deadlines, and devised a slot allocation scheme for allocating pre-arbitrated (PA) slots to isochronous message streams in DQDB networks. In this paper, we extend our work and address on how to improve the performance (in terms of bandwidth utilization) of the slot allocation scheme using the concept of slot reuse. We devise several slot reuse schemes to assign spatially non-intersecting message streams to the same virtual connections (i.e., the sets of PA slots identified by the same VCI numbers). The proposed slot reuse schemes are simple, can be easily incorporated into the slot allocation scheme described previously, and require only a minor change in the current DQDB standards.
{"title":"On slot reuse for isochronous services in DQDB networks","authors":"C. Han, J. Hou, K. Shin","doi":"10.1109/REAL.1995.495212","DOIUrl":"https://doi.org/10.1109/REAL.1995.495212","url":null,"abstract":"DQDB is a MAC protocol jointly adopted by IEEE and ANSI as the candidate protocol for MANs, and has been studied by many researchers. Previously, we laid a formal basis for guaranteeing the timely delivery of isochronous (real-time) messages with hard deadlines, and devised a slot allocation scheme for allocating pre-arbitrated (PA) slots to isochronous message streams in DQDB networks. In this paper, we extend our work and address on how to improve the performance (in terms of bandwidth utilization) of the slot allocation scheme using the concept of slot reuse. We devise several slot reuse schemes to assign spatially non-intersecting message streams to the same virtual connections (i.e., the sets of PA slots identified by the same VCI numbers). The proposed slot reuse schemes are simple, can be easily incorporated into the slot allocation scheme described previously, and require only a minor change in the current DQDB standards.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124736004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495190
S. Nadjm-Tehrani, Jan-Erik Strömberg
We give an exposition to an ongoing research effort in cooperation with aerospace industries in Sweden. We report on an application of formal verification techniques on a landing gear system. This system consists of actuating hydromechanic and electromechanic hardware, and of controlling software components. We emphasize the need for modelling techniques and languages covering the whole spectrum from informal engineering documents, to hybrid mathematical models. In this modelling process we give as much weight to the physical environment as to the controlling software. We show the application of two verification methods for proving safety and timeliness properties of the closed loop system; first, using the proof system of extended duration calculus, and second by symbolic model checking.
{"title":"Proving dynamic properties in an aerospace application","authors":"S. Nadjm-Tehrani, Jan-Erik Strömberg","doi":"10.1109/REAL.1995.495190","DOIUrl":"https://doi.org/10.1109/REAL.1995.495190","url":null,"abstract":"We give an exposition to an ongoing research effort in cooperation with aerospace industries in Sweden. We report on an application of formal verification techniques on a landing gear system. This system consists of actuating hydromechanic and electromechanic hardware, and of controlling software components. We emphasize the need for modelling techniques and languages covering the whole spectrum from informal engineering documents, to hybrid mathematical models. In this modelling process we give as much weight to the physical environment as to the controlling software. We show the application of two verification methods for proving safety and timeliness properties of the closed loop system; first, using the proof system of extended duration calculus, and second by symbolic model checking.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495197
C. Daws, S. Yovine
Multirate timed automata are an extension of timed automata where each clock has its own speed varying between a lower and an upper bound that may change from one control location to another. This formalism is well-suited for specifying hybrid systems where the dynamics of the continuous variables are defined or can be approximated by giving the minimal and maximal rate of change. To avoid the difficulties inherent in the verification of multirate timed automata, we follow an approach that consists of first transforming the multirate timed automata into timed automata and then applying the symbolic techniques implemented in KRONOS. We show the practical interest of this approach analyzing two examples recently proposed in the literature and considered to be realistic case studies: a manufacturing plant and the Philips audio control protocol.
{"title":"Two examples of verification of multirate timed automata with Kronos","authors":"C. Daws, S. Yovine","doi":"10.1109/REAL.1995.495197","DOIUrl":"https://doi.org/10.1109/REAL.1995.495197","url":null,"abstract":"Multirate timed automata are an extension of timed automata where each clock has its own speed varying between a lower and an upper bound that may change from one control location to another. This formalism is well-suited for specifying hybrid systems where the dynamics of the continuous variables are defined or can be approximated by giving the minimal and maximal rate of change. To avoid the difficulties inherent in the verification of multirate timed automata, we follow an approach that consists of first transforming the multirate timed automata into timed automata and then applying the symbolic techniques implemented in KRONOS. We show the practical interest of this approach analyzing two examples recently proposed in the literature and considered to be realistic case studies: a manufacturing plant and the Philips audio control protocol.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121590671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495218
Christopher A. Healy, D. Whalley, M. Harmon
Recently designed machines contain pipelines and caches. While both features provide significant performance advantages, they also pose problems for predicting execution time of code segments in real-time systems. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss depends on the dynamic sequence of previous instructions executed and memory references performed. Furthermore, these penalties are not independent since delays due to pipeline stalls and cache miss penalties may overlap. This paper describes an approach for bounding the worst-case performance of large code segments on machines that exploit both pipelining and instruction caching. First, a method is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. Next, these categorizations are used in the pipeline analysis of sequences of instructions representing paths within the program. A timing analyzer uses the pipeline path analysis to estimate the worst-case execution performance of each loop and function in the program. Finally, a graphical user interface is invoked that allows a user to request timing predictions on portions of the program.
{"title":"Integrating the timing analysis of pipelining and instruction caching","authors":"Christopher A. Healy, D. Whalley, M. Harmon","doi":"10.1109/REAL.1995.495218","DOIUrl":"https://doi.org/10.1109/REAL.1995.495218","url":null,"abstract":"Recently designed machines contain pipelines and caches. While both features provide significant performance advantages, they also pose problems for predicting execution time of code segments in real-time systems. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss depends on the dynamic sequence of previous instructions executed and memory references performed. Furthermore, these penalties are not independent since delays due to pipeline stalls and cache miss penalties may overlap. This paper describes an approach for bounding the worst-case performance of large code segments on machines that exploit both pipelining and instruction caching. First, a method is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. Next, these categorizations are used in the pipeline analysis of sequences of instructions representing paths within the program. A timing analyzer uses the pipeline path analysis to estimate the worst-case execution performance of each loop and function in the program. Finally, a graphical user interface is invoked that allows a user to request timing predictions on portions of the program.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116135495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495198
K. Larsen, P. Pettersson, W. Yi
Efficient automatic model-checking algorithms for real-time systems have been obtained in recent years based on the state-region graph technique of Alur, Courcoubetis and Dill (1990). However, these algorithms are faced with two potential types of explosion arising from parallel composition: explosion in the space of control nodes, and explosion in the region space over clock-variables. In this paper we attack these explosion problems by developing and combining compositional and symbolic model-checking techniques. The presented techniques provide the foundation for a new automatic verification tool UPPAAL. Experimental results indicate that UPPAAL performs time- and space-wise favorably compared with other real-time verification tools.
{"title":"Compositional and symbolic model-checking of real-time systems","authors":"K. Larsen, P. Pettersson, W. Yi","doi":"10.1109/REAL.1995.495198","DOIUrl":"https://doi.org/10.1109/REAL.1995.495198","url":null,"abstract":"Efficient automatic model-checking algorithms for real-time systems have been obtained in recent years based on the state-region graph technique of Alur, Courcoubetis and Dill (1990). However, these algorithms are faced with two potential types of explosion arising from parallel composition: explosion in the space of control nodes, and explosion in the region space over clock-variables. In this paper we attack these explosion problems by developing and combining compositional and symbolic model-checking techniques. The presented techniques provide the foundation for a new automatic verification tool UPPAAL. Experimental results indicate that UPPAAL performs time- and space-wise favorably compared with other real-time verification tools.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129391947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495194
M. Humphrey, G. Wallace, J. Stankovic
The design of a kernel-level thread package for dynamic, hard real-time environments is presented. A highly integrated design is used to ensure predictability. A system description language and real-time programming language are used to specify key properties of threads and thread groups. For a thread, this includes whether or not the thread spawns other threads at run-time, the type of performance guarantee the thread requires, how the thread interacts with other threads, and what processors the thread may execute on. A predictable kernel uses this information along with on-line dynamic guarantees to ensure predictable execution of threads. The first phase of the thread package has been implemented and performance measurements have indicated a 66% improvement in context switching costs.
{"title":"Kernel-level threads for dynamic, hard real-time environments","authors":"M. Humphrey, G. Wallace, J. Stankovic","doi":"10.1109/REAL.1995.495194","DOIUrl":"https://doi.org/10.1109/REAL.1995.495194","url":null,"abstract":"The design of a kernel-level thread package for dynamic, hard real-time environments is presented. A highly integrated design is used to ensure predictability. A system description language and real-time programming language are used to specify key properties of threads and thread groups. For a thread, this includes whether or not the thread spawns other threads at run-time, the type of performance guarantee the thread requires, how the thread interacts with other threads, and what processors the thread may execute on. A predictable kernel uses this information along with on-line dynamic guarantees to ensure predictable execution of threads. The first phase of the thread package has been implemented and performance measurements have indicated a 66% improvement in context switching costs.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122211669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-05DOI: 10.1109/REAL.1995.495204
Biao Chen, S. Kamat, Wei Zhao
FDDI-Based Reconfigurable Networks have an architecture that is suitable for delivering messages that have hard real-time constraints as well as certain fault-tolerance requirements. This architecture uses multiple FDDI networks to connect hosts and provides for automatic reconfiguration to maintain high network bandwidth in spite of faults. An important open problem is how resources in such networks should be managed in order to guarantee that the fault-tolerant real-time requirements of messages are met. This paper presents an efficient and practical solution to this problem. Our solution consists of off-line and on-line components. On-line management deals with run-time manipulation of messages and network resources. A message grouping approach simplifies on-line management. Off-line management deals with message grouping, bandwidth allocation and schedulability verification. Three approaches are investigated: spatial redundancy, temporal redundancy and an integrated approach. It is shown that the integrated approach has the best performance. Our solution is compatible with the FDDI and SAFENET standards.
{"title":"Fault-tolerant real-time communication in FDDI-based networks","authors":"Biao Chen, S. Kamat, Wei Zhao","doi":"10.1109/REAL.1995.495204","DOIUrl":"https://doi.org/10.1109/REAL.1995.495204","url":null,"abstract":"FDDI-Based Reconfigurable Networks have an architecture that is suitable for delivering messages that have hard real-time constraints as well as certain fault-tolerance requirements. This architecture uses multiple FDDI networks to connect hosts and provides for automatic reconfiguration to maintain high network bandwidth in spite of faults. An important open problem is how resources in such networks should be managed in order to guarantee that the fault-tolerant real-time requirements of messages are met. This paper presents an efficient and practical solution to this problem. Our solution consists of off-line and on-line components. On-line management deals with run-time manipulation of messages and network resources. A message grouping approach simplifies on-line management. Off-line management deals with message grouping, bandwidth allocation and schedulability verification. Three approaches are investigated: spatial redundancy, temporal redundancy and an integrated approach. It is shown that the integrated approach has the best performance. Our solution is compatible with the FDDI and SAFENET standards.","PeriodicalId":231426,"journal":{"name":"Proceedings 16th IEEE Real-Time Systems Symposium","volume":"5 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130072906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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