Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533897
D. Andrews, M. Platzner
Our semiconductor industry is ushering in the era of the reconfigurable manycore chip to increase the energy efficiency of computing irregular parallelism within large and power hungry data centers. If reconfigurable manycores are to become part of the mainstream narrative for next generation data center and warehouse scale computers, the large cadre of software programmers must be given access to these devices through their accepted programming models. In this paper we present an overview of two prior projects called hthreads and ReconOS, that both successfully unified computations that ran as hardware threads in the FPGA with software threads on fixed ISA components under the multithreaded programming model. We discuss the design tradeoffs that were made and resulting implementation details of these two systems. We then project how aspects of both systems may provide important insights for system architectets and system software developers for bringing evolving reconfigurable manycores under the virtualization ecosystems used within datacenters.
{"title":"Programming models for reconfigurable manycore systems","authors":"D. Andrews, M. Platzner","doi":"10.1109/ReCoSoC.2016.7533897","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533897","url":null,"abstract":"Our semiconductor industry is ushering in the era of the reconfigurable manycore chip to increase the energy efficiency of computing irregular parallelism within large and power hungry data centers. If reconfigurable manycores are to become part of the mainstream narrative for next generation data center and warehouse scale computers, the large cadre of software programmers must be given access to these devices through their accepted programming models. In this paper we present an overview of two prior projects called hthreads and ReconOS, that both successfully unified computations that ran as hardware threads in the FPGA with software threads on fixed ISA components under the multithreaded programming model. We discuss the design tradeoffs that were made and resulting implementation details of these two systems. We then project how aspects of both systems may provide important insights for system architectets and system software developers for bringing evolving reconfigurable manycores under the virtualization ecosystems used within datacenters.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124138847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533911
W. Harrison, I. Graves, A. Procter, M. Becchi, G. Allwein
FPGA programmability remains a concern with respect to the broad adoption of the technology. One reason for this is simple: FPGA applications are frequently implementations of concurrent algorithms that could be most directly rendered in concurrent languages, but there is little or no first-class support for concurrent applications in conventional hardware description languages. It stands to reason that FPGA programmability would be enhanced in a hardware description language with first-class concurrency. The starting point for this paper is a functional hardware description language with built-in support for concurrency called ReWire. Because it is a concurrent functional language, ReWire supports the elegant expression of common concurrency paradigms; we illustrate this with several case studies.
{"title":"A programming model for reconfigurable computing based in functional concurrency","authors":"W. Harrison, I. Graves, A. Procter, M. Becchi, G. Allwein","doi":"10.1109/ReCoSoC.2016.7533911","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533911","url":null,"abstract":"FPGA programmability remains a concern with respect to the broad adoption of the technology. One reason for this is simple: FPGA applications are frequently implementations of concurrent algorithms that could be most directly rendered in concurrent languages, but there is little or no first-class support for concurrent applications in conventional hardware description languages. It stands to reason that FPGA programmability would be enhanced in a hardware description language with first-class concurrency. The starting point for this paper is a functional hardware description language with built-in support for concurrency called ReWire. Because it is a concurrent functional language, ReWire supports the elegant expression of common concurrency paradigms; we illustrate this with several case studies.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124756995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533908
J. Joseph, Sven Wrieden, Christopher Blochwitz, A. Ortiz, Thilo Pionteck
We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple design metrics is mandatory. Our simulation environment consists of three parts. First, it comprises a NoC simulator that supports a multitude of different manufacturing technologies, router architectures, and network topologies within a single design. As a key feature, the NoC and technologies parameters per chip layer are fully configurable during simulation runtime permitting flexible and fast evaluation. Second, a central reporting tool facilitates system analysis on different abstraction levels. Third, the evolution tool provides various synthetic and real-world based benchmarks. Thus, our tool allows for an incremental approach to systematically explore the A-3D-NoC's design space.
我们提出了一个全面的模拟环境，用于非对称3d片上网络(a - 3d - noc)的设计空间探索，涵盖了3d片上系统(3d - soc)的异质性。A- 3d - noc设计的一个具有挑战性的方面是考虑通信基础设施的交织参数和制造技术的特点。因此，同时评估多个设计度量是必须的。我们的仿真环境由三部分组成。首先，它包含一个NoC模拟器，该模拟器在单个设计中支持多种不同的制造技术、路由器架构和网络拓扑结构。作为一个关键特性，每个芯片层的NoC和技术参数在仿真运行时是完全可配置的，允许灵活和快速的评估。其次，中心报告工具有助于在不同抽象层次上进行系统分析。第三，演进工具提供了各种综合的和基于现实世界的基准。因此，我们的工具允许系统地探索A-3D-NoC的设计空间的增量方法。
{"title":"A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip","authors":"J. Joseph, Sven Wrieden, Christopher Blochwitz, A. Ortiz, Thilo Pionteck","doi":"10.1109/ReCoSoC.2016.7533908","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533908","url":null,"abstract":"We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple design metrics is mandatory. Our simulation environment consists of three parts. First, it comprises a NoC simulator that supports a multitude of different manufacturing technologies, router architectures, and network topologies within a single design. As a key feature, the NoC and technologies parameters per chip layer are fully configurable during simulation runtime permitting flexible and fast evaluation. Second, a central reporting tool facilitates system analysis on different abstraction levels. Third, the evolution tool provides various synthetic and real-world based benchmarks. Thus, our tool allows for an incremental approach to systematically explore the A-3D-NoC's design space.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533898
Martha Johanna Sepúlveda, Daniel Flórez, Ramon Fernandes, C. Marcon, G. Gogniat, G. Sigl
Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are currently exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infecting IP-blocks connected to a Network-on-Chip (NoC) and opening doors to perform Timing Side Channel Attacks (TSCA). By monitoring the NoC traffic, an attacker is able to infer the sensitive information, such as secret keys. Previous works have shown that NoC routing can be used to avoid attacks. In this paper we propose GRaNoC, a NoC architecture able to monitor and evaluate the risk of the communication paths inside the NoC. Sensitive traffic is exchanged to minimal low-risk paths defined at runtime. We propose five types of dead-lock free risk-aware routing algorithm and evaluate the security, performance and cost under several synthetic and SPLASH-2 benchmarks. We show that our architecture is able to guarantee secure paths during runtime while adding only low cost and performance penalties to the MPSoC.
{"title":"Towards risk aware NoCs for data protection in MPSoCs","authors":"Martha Johanna Sepúlveda, Daniel Flórez, Ramon Fernandes, C. Marcon, G. Gogniat, G. Sigl","doi":"10.1109/ReCoSoC.2016.7533898","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533898","url":null,"abstract":"Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are currently exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infecting IP-blocks connected to a Network-on-Chip (NoC) and opening doors to perform Timing Side Channel Attacks (TSCA). By monitoring the NoC traffic, an attacker is able to infer the sensitive information, such as secret keys. Previous works have shown that NoC routing can be used to avoid attacks. In this paper we propose GRaNoC, a NoC architecture able to monitor and evaluate the risk of the communication paths inside the NoC. Sensitive traffic is exchanged to minimal low-risk paths defined at runtime. We propose five types of dead-lock free risk-aware routing algorithm and evaluate the security, performance and cost under several synthetic and SPLASH-2 benchmarks. We show that our architecture is able to guarantee secure paths during runtime while adding only low cost and performance penalties to the MPSoC.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125658368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533900
M. M. Real, P. Wehner, Vincent Migliore, Vianney Lapôtre, D. Göhringer, G. Gogniat
Many-core architectures are becoming a major execution platform in order to face the increasing number of applications executed in parallel. While these architectures provide massive parallelism and high performance to the users, they also introduce key challenges in terms of security. Indeed, in order to leverage performance, a great number of applications running in parallel may share resources. A malicious application may compromise other applications sharing common resources or the whole system by directly accessing, deducing or retrieving sensitive data. This work focuses on a many-core accelerator architecture extended with mechanisms allowing the logical and spatial isolation of sensitive applications through the dynamic creation of secure zones. Each sensitive application is executed within a secure zone avoiding any resource sharing with other potentially malicious applications, preventing denial of services within the secure zones as well as confidentiality and integrity attacks. A set of services guarantying the dynamic creation and handling of spatially isolated secure zones in a many-core accelerator architecture is proposed. These services are integrated into a software controller on a many-core accelerator architecture and evaluated through virtual prototyping.
{"title":"Dynamic spatially isolated secure zones for NoC-based many-core accelerators","authors":"M. M. Real, P. Wehner, Vincent Migliore, Vianney Lapôtre, D. Göhringer, G. Gogniat","doi":"10.1109/ReCoSoC.2016.7533900","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533900","url":null,"abstract":"Many-core architectures are becoming a major execution platform in order to face the increasing number of applications executed in parallel. While these architectures provide massive parallelism and high performance to the users, they also introduce key challenges in terms of security. Indeed, in order to leverage performance, a great number of applications running in parallel may share resources. A malicious application may compromise other applications sharing common resources or the whole system by directly accessing, deducing or retrieving sensitive data. This work focuses on a many-core accelerator architecture extended with mechanisms allowing the logical and spatial isolation of sensitive applications through the dynamic creation of secure zones. Each sensitive application is executed within a secure zone avoiding any resource sharing with other potentially malicious applications, preventing denial of services within the secure zones as well as confidentiality and integrity attacks. A set of services guarantying the dynamic creation and handling of spatially isolated secure zones in a many-core accelerator architecture is proposed. These services are integrated into a software controller on a many-core accelerator architecture and evaluated through virtual prototyping.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129783299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533903
Siavoosh Payandeh Azad, Behrad Niazmand, P. Ellervee, J. Raik, G. Jervan, T. Hollstein
In this paper, an open-source framework for task deployment of mixed-critical and non-critical applications under dependability constraints in Network-on-Chip (NoC) based systems is introduced. This system level design space exploration is guided by a System Health Monitoring Unit which keeps a holistic view of system health status. The framework supports task clustering, mapping and scheduling of different applications, using different heuristics, on a NoC-based architecture which can have different topologies. This enables exploration of 2D and 3D typologies, any turn model based routing algorithm, fault monitoring mechanisms and different fault models (Link, Turn, Node).
{"title":"SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints","authors":"Siavoosh Payandeh Azad, Behrad Niazmand, P. Ellervee, J. Raik, G. Jervan, T. Hollstein","doi":"10.1109/ReCoSoC.2016.7533903","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533903","url":null,"abstract":"In this paper, an open-source framework for task deployment of mixed-critical and non-critical applications under dependability constraints in Network-on-Chip (NoC) based systems is introduced. This system level design space exploration is guided by a System Health Monitoring Unit which keeps a holistic view of system health status. The framework supports task clustering, mapping and scheduling of different applications, using different heuristics, on a NoC-based architecture which can have different topologies. This enables exploration of 2D and 3D typologies, any turn model based routing algorithm, fault monitoring mechanisms and different fault models (Link, Turn, Node).","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128672555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533894
Tripti Jain, K. Schneider, Anoop Bhagyanath
This paper introduces with the selector-tree network a new self-routing and non-blocking interconnection network: The n × n network is capable of routing any permutation of its n inputs to its n output ports and is therefore non-blocking, and thus, more powerful than Ω-permutation and Banyan networks. In contrast to other non-blocking interconnection networks like the Beneš network, our selector-tree network does not need an additional setup time since the target addresses of the connections directly define the conflict-free routes so that the network is self-routing. The overall depth of the network depends on the implementation of its building block, the selector module: In this paper, we present two preliminary alternatives where the more expensive one requires O(log(n)2) time and O(n2 log(n)) gates while the other one requires O(n) cycles and only O(n) gates for the n × n network. The two alternatives can also be combined to optimize both time and size for particular sizes.
{"title":"The selector-tree network: A new self-routing and non-blocking interconnection network","authors":"Tripti Jain, K. Schneider, Anoop Bhagyanath","doi":"10.1109/ReCoSoC.2016.7533894","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533894","url":null,"abstract":"This paper introduces with the selector-tree network a new self-routing and non-blocking interconnection network: The n × n network is capable of routing any permutation of its n inputs to its n output ports and is therefore non-blocking, and thus, more powerful than Ω-permutation and Banyan networks. In contrast to other non-blocking interconnection networks like the Beneš network, our selector-tree network does not need an additional setup time since the target addresses of the connections directly define the conflict-free routes so that the network is self-routing. The overall depth of the network depends on the implementation of its building block, the selector module: In this paper, we present two preliminary alternatives where the more expensive one requires O(log(n)2) time and O(n2 log(n)) gates while the other one requires O(n) cycles and only O(n) gates for the n × n network. The two alternatives can also be combined to optimize both time and size for particular sizes.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130426912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533912
Ayad Dalloo, A. Ortiz
Binary-image processing cores are extremely useful in many image and video applications such as object recognition, tracking, motion detection, and identification. To address the variety of applications and binary-image kernels, we propose an FPGA-based intellectual property core with enhanced flexibility: it is programmable, reconfigurable, and parameterizable. The core performs single binary image kernels (morphological operations) and even complete algorithms composed by sequences of operations; the algorithms' control does not require an external processor as in previous approaches. The reconfiguration features allow adapting the image size, structuring element, and even image parallelism for some operations at run-time. Finally, the parameterization allows defining the maximum image, feature, and command-buffer sizes as well as the number of pixel processing units at compile time. The careful combination of programmability, reconfigurability, and parameterization produces a flexible yet efficient binary-image processing architecture. A detailed experimental validation using a Virtex 5 platform assesses the advantages of the proposed architecture versus previous approaches. The results show that the core can process about 1500 frames per second for 32 operations for a 1024 × 1024 image and 5×5 structure-element at 100MHz frequency. The results demonstrate that the core is suitable for real-time binary image processing applications.
{"title":"A programmable and reconfigurable core for binary image processing","authors":"Ayad Dalloo, A. Ortiz","doi":"10.1109/ReCoSoC.2016.7533912","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533912","url":null,"abstract":"Binary-image processing cores are extremely useful in many image and video applications such as object recognition, tracking, motion detection, and identification. To address the variety of applications and binary-image kernels, we propose an FPGA-based intellectual property core with enhanced flexibility: it is programmable, reconfigurable, and parameterizable. The core performs single binary image kernels (morphological operations) and even complete algorithms composed by sequences of operations; the algorithms' control does not require an external processor as in previous approaches. The reconfiguration features allow adapting the image size, structuring element, and even image parallelism for some operations at run-time. Finally, the parameterization allows defining the maximum image, feature, and command-buffer sizes as well as the number of pixel processing units at compile time. The careful combination of programmability, reconfigurability, and parameterization produces a flexible yet efficient binary-image processing architecture. A detailed experimental validation using a Virtex 5 platform assesses the advantages of the proposed architecture versus previous approaches. The results show that the core can process about 1500 frames per second for 32 operations for a 1024 × 1024 image and 5×5 structure-element at 100MHz frequency. The results demonstrate that the core is suitable for real-time binary image processing applications.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"885 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134401723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533905
Poona Bahrebar, D. Stroobandt
As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more susceptible to faults. Resiliency to device failures is, therefore, a key objective in the design of the Systems-on-Chip (SoCs). This paper seeks to address reliability by presenting a routing algorithm for 2D mesh NoCs. Using the proposed method which is designed based on the Abacus Turn Model (AbTM), the healthy paths can be dynamically configured according to the location of faults and congestion in the network. As a result, not only the functionality of the network is maintained in the vicinity of faults, but also a high performance communication can be provided. The presented technique is an adaptive, distributed, deadlock-free, and congestion-aware routing method which does not require routing tables or virtual channels. The experimental results demonstrate the reliability of NoC against multiple link failures with a small hardware overhead penalty.
{"title":"Online reconfigurable routing method for handling link failures in NoC-based MPSoCs","authors":"Poona Bahrebar, D. Stroobandt","doi":"10.1109/ReCoSoC.2016.7533905","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533905","url":null,"abstract":"As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more susceptible to faults. Resiliency to device failures is, therefore, a key objective in the design of the Systems-on-Chip (SoCs). This paper seeks to address reliability by presenting a routing algorithm for 2D mesh NoCs. Using the proposed method which is designed based on the Abacus Turn Model (AbTM), the healthy paths can be dynamically configured according to the location of faults and congestion in the network. As a result, not only the functionality of the network is maintained in the vicinity of faults, but also a high performance communication can be provided. The presented technique is an adaptive, distributed, deadlock-free, and congestion-aware routing method which does not require routing tables or virtual channels. The experimental results demonstrate the reliability of NoC against multiple link failures with a small hardware overhead penalty.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133546679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/ReCoSoC.2016.7533907
L. Sterpone, L. Boragno, D. M. Codinachs
SRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault injection and fault emulation and configuration scrubbing, has been carried out over three versions of a reconfigurable Fast Fourier Transform (FFT) system: a single FFT, a single larger FFT and a FFT with TMR architecture. The analysis has been focused on multiple injected SEUs scenario, considering the availability problem in a real-time application and highlighting the circuit tolerance at the upset presence. This operation has the goal to emulate as much as possible a real radiation test avoiding all the handicaps that this procedure involves. The obtained results have shown the advantages of the configuration scrubbing performed with the aim to fix multiple upsets, achieving up to 13.6% of circuit hardening. The achieved conclusions are an interesting starting point for the study of fault mitigation techniques through the use of reconfiguration. The projects have been tested on a Z-7010 AP SoC.
基于sram的fpga广泛应用于空间和航空电子计算中。不友好的环境和FPGA对辐射的敏感性会对应用的可靠性造成严重的影响。部分自重构能力提供了一个很好的帮助，以抵消单事件扰动(SEUs)引起的过度硅电离，以及随之而来的系统行为不当。与此特性相关的故障注入、故障仿真和配置清洗已经在可重构快速傅里叶变换(FFT)系统的三个版本上进行:单个FFT、单个较大FFT和具有TMR架构的FFT。分析的重点是多注入seu场景，考虑了实时应用中的可用性问题，并强调了扰动存在时的电路容限。该手术的目标是尽可能模拟真实的辐射测试，避免该手术所涉及的所有障碍。所获得的结果表明，为了修复多次镦粗而进行的配置洗涤具有优势，可实现高达13.6%的回路硬化。所获得的结论是通过使用重构来研究故障缓解技术的一个有趣的起点。这些项目已经在Z-7010 AP SoC上进行了测试。
{"title":"Analysis of radiation-induced SEUs on dynamic reconfigurable systems","authors":"L. Sterpone, L. Boragno, D. M. Codinachs","doi":"10.1109/ReCoSoC.2016.7533907","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533907","url":null,"abstract":"SRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault injection and fault emulation and configuration scrubbing, has been carried out over three versions of a reconfigurable Fast Fourier Transform (FFT) system: a single FFT, a single larger FFT and a FFT with TMR architecture. The analysis has been focused on multiple injected SEUs scenario, considering the availability problem in a real-time application and highlighting the circuit tolerance at the upset presence. This operation has the goal to emulate as much as possible a real radiation test avoiding all the handicaps that this procedure involves. The obtained results have shown the advantages of the configuration scrubbing performed with the aim to fix multiple upsets, achieving up to 13.6% of circuit hardening. The achieved conclusions are an interesting starting point for the study of fault mitigation techniques through the use of reconfiguration. The projects have been tested on a Z-7010 AP SoC.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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