Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307426
P. Pavón-Mariño, J. Veiga-Gontán, A. Ortuno-Manzanera, W. Cerroni, J. García-Haro
This paper presents the PI-OBS algorithm, a parallel-iterative scheduler for OBS nodes. Conventional schemes are greedy in the sense that they process headers one by one. In PI-OBS, all the headers received during a given time window are jointly processed to optimize the delay and output wavelength allocation, applying void filling techniques, and allowing traffic differentiation. Results show a similar or better performance than the LAUC-VF algorithm, commonly used as a performance bound for OBS schedulers. The PI-OBS scheduler has been designed to allow parallel electronic implementation similar to the ones in VOQ schedulers, with a deterministic response time.
{"title":"PI-OBS: a parallel iterative optical burst scheduler for OBS networks","authors":"P. Pavón-Mariño, J. Veiga-Gontán, A. Ortuno-Manzanera, W. Cerroni, J. García-Haro","doi":"10.1109/HPSR.2009.5307426","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307426","url":null,"abstract":"This paper presents the PI-OBS algorithm, a parallel-iterative scheduler for OBS nodes. Conventional schemes are greedy in the sense that they process headers one by one. In PI-OBS, all the headers received during a given time window are jointly processed to optimize the delay and output wavelength allocation, applying void filling techniques, and allowing traffic differentiation. Results show a similar or better performance than the LAUC-VF algorithm, commonly used as a performance bound for OBS schedulers. The PI-OBS scheduler has been designed to allow parallel electronic implementation similar to the ones in VOQ schedulers, with a deterministic response time.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131807072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307427
I. Sourdis, Ruben De Smet, G. Gaydadjiev
In this paper we introduce a new data structure for address lookup, a new tree structure which improves on the existing Range Trees allowing shorter comparisons than the address width. The proposed scheme shares among multiple concurrent comparisons common address prefixes and suffixes and also omits address parts not required for computing a next node branch. In so doing, for a given memory bandwidth, we achieve a larger number of concurrent comparisons than the original Range Tree. This results in less memory accesses and lower latency per lookup. Performance scales better as the address width and the number of address ranges increase. We describe the rules employed to construct the proposed structure and offer two heuristics which generate the “configuration” of the decision tree given a set of address ranges. The proposed Range Tree with variable-length comparisons (RT-VLC) has up to 50% less tree-levels than the original Range Tree and its memory requirements are 50% to 2× that of a linear search approach.
{"title":"Range Trees with variable length comparisons","authors":"I. Sourdis, Ruben De Smet, G. Gaydadjiev","doi":"10.1109/HPSR.2009.5307427","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307427","url":null,"abstract":"In this paper we introduce a new data structure for address lookup, a new tree structure which improves on the existing Range Trees allowing shorter comparisons than the address width. The proposed scheme shares among multiple concurrent comparisons common address prefixes and suffixes and also omits address parts not required for computing a next node branch. In so doing, for a given memory bandwidth, we achieve a larger number of concurrent comparisons than the original Range Tree. This results in less memory accesses and lower latency per lookup. Performance scales better as the address width and the number of address ranges increase. We describe the rules employed to construct the proposed structure and offer two heuristics which generate the “configuration” of the decision tree given a set of address ranges. The proposed Range Tree with variable-length comparisons (RT-VLC) has up to 50% less tree-levels than the original Range Tree and its memory requirements are 50% to 2× that of a linear search approach.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307421
S. Hauger
Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability at registertransfer level providing fine grain adaptability to unforeseen processing requirements and a high processing power. The latter are programmed at the more abstract software level and support high-speed execution of their fixed set of instructions. In this paper, we present a novel architecture for an FPGA-based highspeed network processing unit offering programmable modules at multiple levels of abstraction: register-transfer level, microcode level, software level and parameter level. A prototypical implementation demonstrates its feasibility with today's field programmable gate array devices offering a throughput of more than one hundred million minimum sized packets per second.
{"title":"A novel architecture for a high-performance network processing unit: Flexibility at multiple levels of abstraction","authors":"S. Hauger","doi":"10.1109/HPSR.2009.5307421","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307421","url":null,"abstract":"Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability at registertransfer level providing fine grain adaptability to unforeseen processing requirements and a high processing power. The latter are programmed at the more abstract software level and support high-speed execution of their fixed set of instructions. In this paper, we present a novel architecture for an FPGA-based highspeed network processing unit offering programmable modules at multiple levels of abstraction: register-transfer level, microcode level, software level and parameter level. A prototypical implementation demonstrates its feasibility with today's field programmable gate array devices offering a throughput of more than one hundred million minimum sized packets per second.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307440
Dong Lin, M. Hamdi
With the continuous advances in communications technology, the link transmission speed of the Internet backbone networks has been increasing rapidly. This in turn demands more powerful IP address lookup engines. Being well-suited for high performance parallel lookup, Ternary Content Addressable Memory (TCAM) has been widely used in this area for years. Nevertheless, the limited storage, high power consumption and expensive price restrict its further application as link rates increase. Motivated by the prevalence of cheaper and faster conventional memory, such as SRAM and DRAM, we propose a range-based partitioning algorithm called “Max-splitting” which divides the entire route table into several sub-tries with disjoint range boundaries. With an extra index and a new lookup structure called Memory Filter, some sub-tries could be stored outside the TCAM. The experiments on real-life BGP route table will demonstrate that, by allocating little more conventional memory space, the proposed scheme reduces the TCAM storage requirement by 92% and significantly cuts down the power consumption.
{"title":"Compress the route table stored in TCAM by using memory filter","authors":"Dong Lin, M. Hamdi","doi":"10.1109/HPSR.2009.5307440","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307440","url":null,"abstract":"With the continuous advances in communications technology, the link transmission speed of the Internet backbone networks has been increasing rapidly. This in turn demands more powerful IP address lookup engines. Being well-suited for high performance parallel lookup, Ternary Content Addressable Memory (TCAM) has been widely used in this area for years. Nevertheless, the limited storage, high power consumption and expensive price restrict its further application as link rates increase. Motivated by the prevalence of cheaper and faster conventional memory, such as SRAM and DRAM, we propose a range-based partitioning algorithm called “Max-splitting” which divides the entire route table into several sub-tries with disjoint range boundaries. With an extra index and a new lookup structure called Memory Filter, some sub-tries could be stored outside the TCAM. The experiments on real-life BGP route table will demonstrate that, by allocating little more conventional memory space, the proposed scheme reduces the TCAM storage requirement by 92% and significantly cuts down the power consumption.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"502 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127594278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307436
Pawel Korus, F. Paolucci, L. Valcarenghi, F. Cugini, P. Castoldi, M. Kantor, K. Wajda
When dynamic service interconnection requests are managed by a centralized system (e.g., a network management system — NMS), the time required for the connections to be fully operational might be heavily impacted by the policy utilized to serve them. The policies must be devised for mitigating issues that increase this time, such as commercial router irresponsiveness to configuration commands during configuration commit. In this paper a batch provisioning policy is proposed to be implemented in a Grid-augmented NMS (GNMS) to serve grid computing clients interconnection requests and mitigate router irresposiveness. Based on the proposed policy, requests are queued in the GNMS and they are activated in a batch, based on a time-out. The proposed batch provisioning policy is experimentally compared to a per-request provisioning policy that serves the requests as soon as they are received by the GNMS. Experimental evaluation results show that, when connection requests are not rare, the average time elapsing between the reception of a connection request by the GNMS and the connection being fully operational (i.e., the service time) is much shorter, on average, if batch provisioning policy is utilized.
{"title":"Experimental evaluation of batch versus per-request service interconnection activation in PCE-based Grid networking","authors":"Pawel Korus, F. Paolucci, L. Valcarenghi, F. Cugini, P. Castoldi, M. Kantor, K. Wajda","doi":"10.1109/HPSR.2009.5307436","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307436","url":null,"abstract":"When dynamic service interconnection requests are managed by a centralized system (e.g., a network management system — NMS), the time required for the connections to be fully operational might be heavily impacted by the policy utilized to serve them. The policies must be devised for mitigating issues that increase this time, such as commercial router irresponsiveness to configuration commands during configuration commit. In this paper a batch provisioning policy is proposed to be implemented in a Grid-augmented NMS (GNMS) to serve grid computing clients interconnection requests and mitigate router irresposiveness. Based on the proposed policy, requests are queued in the GNMS and they are activated in a batch, based on a time-out. The proposed batch provisioning policy is experimentally compared to a per-request provisioning policy that serves the requests as soon as they are received by the GNMS. Experimental evaluation results show that, when connection requests are not rare, the average time elapsing between the reception of a connection request by the GNMS and the connection being fully operational (i.e., the service time) is much shorter, on average, if batch provisioning policy is utilized.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"30 13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125589217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307441
A. Bianco, Daniela Camerino, D. Cuda, F. Neri
The rapid growth of the Internet traffic demand is bringing the current electronic switches closer to their intrinsic technological limits, which may be overcome by optical technologies. Although optical packet switching has been widely studied in academia; the limited processing and buffering capabilities available in the optical domain makes the implementation of an all optical packet switch difficult in practice. We considered a hybrid (electro/optic) switching architecture, relying on an all-optical switching fabric, aiming to understanding the tradeoffs between current photonic and electronic technologies. We consider both the classical fixed-size synchronous paradigm and the asynchronous operation mode, which may suit better to the optical technologies. Buffers organized according to either an electronic FIFO (First Input First Output) paradigm or a photonic FDL (Fiber Delay Line) mechanism are analyzed and compared.
{"title":"Optics vs. electronics in future high-capacity switches/routers","authors":"A. Bianco, Daniela Camerino, D. Cuda, F. Neri","doi":"10.1109/HPSR.2009.5307441","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307441","url":null,"abstract":"The rapid growth of the Internet traffic demand is bringing the current electronic switches closer to their intrinsic technological limits, which may be overcome by optical technologies. Although optical packet switching has been widely studied in academia; the limited processing and buffering capabilities available in the optical domain makes the implementation of an all optical packet switch difficult in practice. We considered a hybrid (electro/optic) switching architecture, relying on an all-optical switching fabric, aiming to understanding the tradeoffs between current photonic and electronic technologies. We consider both the classical fixed-size synchronous paradigm and the asynchronous operation mode, which may suit better to the optical technologies. Buffers organized according to either an electronic FIFO (First Input First Output) paradigm or a photonic FDL (Fiber Delay Line) mechanism are analyzed and compared.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123856820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307417
Arunabha Sen, S. Murthy, Sujogya Banerjee
The studies in fault-tolerance in networks mostly focus on the connectivity of the graph as the metric of faulttolerance. If the underlying graph is k-connected, it can tolerate up to k — 1 failures. In measuring the fault tolerance in terms of connectivity, no assumption regarding the locations of the faulty nodes are made - the failed nodes may be close to each other or far from each other. In other words, the connectivity metric has no way of capturing the notion of locality of faults. However in many networks, faults may be highly localized. This is particularly true in military networks, where an enemy bomb may inflict massive but localized damage to the network. To capture the notion of locality of faults in a network, a new metric region-based connectivity (RBC) was introduced in [1]. It was shown that RBC can achieve the same level of fault-tolerance as the metric connectivity, with much lower networking resources. The study in [1] was restricted to single region fault model (SRFM), where faults are confined to one region only. In this paper, we extend the notion of RBC to multiple region fault model (MRFM), where faults are no longer confined to a single region. As faults in MRFM are still confined to regions, albeit multiple of them, it is different from unconstrained fault model where no constraint on locality of faults is imposed. The MRFM leads to several new concepts, such as region-disjoint paths and region cuts. We show that the classical result, the maximum number of node-disjoint paths between a pair of nodes is equal to the minimum number of nodes whose removal disconnects the pair, is no longer valid when region-disjoint paths and region cuts are considered. We prove that the problems of finding (i) the maximum number of region-disjoint paths between a pair of nodes, and (ii) minimum number of regions whose removal disconnect a pair of nodes, are both NP-complete. We provide heuristic solution to these two problems and evaluate their efficacy by comparing the results with optimal solutions.
{"title":"Region-based connectivity - a new paradigm for design of fault-tolerant networks","authors":"Arunabha Sen, S. Murthy, Sujogya Banerjee","doi":"10.1109/HPSR.2009.5307417","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307417","url":null,"abstract":"The studies in fault-tolerance in networks mostly focus on the connectivity of the graph as the metric of faulttolerance. If the underlying graph is k-connected, it can tolerate up to k — 1 failures. In measuring the fault tolerance in terms of connectivity, no assumption regarding the locations of the faulty nodes are made - the failed nodes may be close to each other or far from each other. In other words, the connectivity metric has no way of capturing the notion of locality of faults. However in many networks, faults may be highly localized. This is particularly true in military networks, where an enemy bomb may inflict massive but localized damage to the network. To capture the notion of locality of faults in a network, a new metric region-based connectivity (RBC) was introduced in [1]. It was shown that RBC can achieve the same level of fault-tolerance as the metric connectivity, with much lower networking resources. The study in [1] was restricted to single region fault model (SRFM), where faults are confined to one region only. In this paper, we extend the notion of RBC to multiple region fault model (MRFM), where faults are no longer confined to a single region. As faults in MRFM are still confined to regions, albeit multiple of them, it is different from unconstrained fault model where no constraint on locality of faults is imposed. The MRFM leads to several new concepts, such as region-disjoint paths and region cuts. We show that the classical result, the maximum number of node-disjoint paths between a pair of nodes is equal to the minimum number of nodes whose removal disconnects the pair, is no longer valid when region-disjoint paths and region cuts are considered. We prove that the problems of finding (i) the maximum number of region-disjoint paths between a pair of nodes, and (ii) minimum number of regions whose removal disconnect a pair of nodes, are both NP-complete. We provide heuristic solution to these two problems and evaluate their efficacy by comparing the results with optimal solutions.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125108658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307428
G. Antichi, A. di Pietro, D. Ficara, S. Giordano, G. Procissi, F. Vitucci
IP address lookup is a fundamental task for Internet routers. Because of the rapid growth of both traffic and links capacity, the time budget to process a packet continues to decrease and lookup tables unceasingly grow; therefore, new algorithms are required to improve lookup performance. However, the large density disparity on the prefix range within real lookup tables suggests a hybrid adaptive technique as effective and simple solution. Therefore, this paper presents a novel approach in which various prefix length ranges are represented with distinct data structures and stored in different memories. In this way, the different frequencies of forwarding rules can be taken in account and the memory hierarchy of real platforms can be exploited. This leads to small structures to be put in fast memory for the most dense ranges and larger structures (with a lower number of accesses) in the slower memories for the other ranges. The results remark the low number of off-chip memory accesses of our scheme and a valuable speedup.
{"title":"A Heuristic and Hybrid Hash-based approach to fast lookup","authors":"G. Antichi, A. di Pietro, D. Ficara, S. Giordano, G. Procissi, F. Vitucci","doi":"10.1109/HPSR.2009.5307428","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307428","url":null,"abstract":"IP address lookup is a fundamental task for Internet routers. Because of the rapid growth of both traffic and links capacity, the time budget to process a packet continues to decrease and lookup tables unceasingly grow; therefore, new algorithms are required to improve lookup performance. However, the large density disparity on the prefix range within real lookup tables suggests a hybrid adaptive technique as effective and simple solution. Therefore, this paper presents a novel approach in which various prefix length ranges are represented with distinct data structures and stored in different memories. In this way, the different frequencies of forwarding rules can be taken in account and the memory hierarchy of real platforms can be exploited. This leads to small structures to be put in fast memory for the most dense ranges and larger structures (with a lower number of accesses) in the slower memories for the other ranges. The results remark the low number of off-chip memory accesses of our scheme and a valuable speedup.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125138955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307425
O. Zadedyurina, Y. Ofek, A. Pattavina
This paper1analyzes the blocking probability of multistage Banyan networks in a combined space and time domain. The analytical solution provides unique tradeoff among various parameters and the corresponding blocking probability. Specifically, this work presents combinatorial based approaches to analyze Banyan in the time domain, which can easily be extended to the WDM domain. The analytical results show that adding time drastically reduces the blocking of (space optimal) Banyan networks. This is significant in general, and in particular, in the optical domain, where the cost of each switching element is high.
{"title":"Combined space and time analysis of Banyan networks","authors":"O. Zadedyurina, Y. Ofek, A. Pattavina","doi":"10.1109/HPSR.2009.5307425","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307425","url":null,"abstract":"This paper1analyzes the blocking probability of multistage Banyan networks in a combined space and time domain. The analytical solution provides unique tradeoff among various parameters and the corresponding blocking probability. Specifically, this work presents combinatorial based approaches to analyze Banyan in the time domain, which can easily be extended to the WDM domain. The analytical results show that adding time drastically reduces the blocking of (space optimal) Banyan networks. This is significant in general, and in particular, in the optical domain, where the cost of each switching element is high.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126058430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307434
K. Nguyen, B. Jaumard
Routers, whose main tasks include forwarding and best route computing, have undergone several design architectures in the last years in order to deal with the explosion of traffic in the Internet. Next generation routers are made with enhanced memory capacity and computing resources, distributed across a very high speed switching fabric. However, the current routing software products, particularly those built by thirdparty developers, are not able to fully exploit the new hardware platform of these routers due to their centralized architectures with a solely control card being responsible for all routing and management tasks. This paper proposes a first fully distributed software architecture of the RSVP-TE module for next generation routers in order to scale with the stringent requirements of the MPLS signaling. The components of the current centralized architecture of RSVP-TE module are offloaded onto line cards in order to share the load between the control card and the line cards. Such a distributed architecture meets the scalability requirements, e.g., high volume of traffic of next generation routers. The robustness and resiliency are also improved. We propose an estimation of the scalability of the distributed RSVP-TE architecture based on the CPU utilization.
{"title":"A distributed and scalable RSVP-TE architecture for next generation IP routers","authors":"K. Nguyen, B. Jaumard","doi":"10.1109/HPSR.2009.5307434","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307434","url":null,"abstract":"Routers, whose main tasks include forwarding and best route computing, have undergone several design architectures in the last years in order to deal with the explosion of traffic in the Internet. Next generation routers are made with enhanced memory capacity and computing resources, distributed across a very high speed switching fabric. However, the current routing software products, particularly those built by thirdparty developers, are not able to fully exploit the new hardware platform of these routers due to their centralized architectures with a solely control card being responsible for all routing and management tasks. This paper proposes a first fully distributed software architecture of the RSVP-TE module for next generation routers in order to scale with the stringent requirements of the MPLS signaling. The components of the current centralized architecture of RSVP-TE module are offloaded onto line cards in order to share the load between the control card and the line cards. Such a distributed architecture meets the scalability requirements, e.g., high volume of traffic of next generation routers. The robustness and resiliency are also improved. We propose an estimation of the scalability of the distributed RSVP-TE architecture based on the CPU utilization.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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