Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307432
Shan Gao, T. Kihara, S. Shimizu, Y. Arakawa, N. Yamanaka, Akifumi Watanabey
This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (Quality of Service). The proposal is an experimental solution with the onchip diorama network, where virtual links and virtual nodes are constructed by some PEs (processing elements). We obtain the realistic traffic fluctuation through the behavior of virtual packets exchanged on the on-chip diorama network. In this paper, as first trial to achieve our final goal, we implemented diorama network and confirmed basic path calculation, where both functions are an essential function of our algorithm. The diorama network traffic engineering can realize more sophisticated network design like adaptive traffic balancing or multi-metric design.
提出了一种基于虚拟节点和虚拟链路的片上立体网络的流量工程方法。立体网络在可重构处理器DAPDNA-2上实现。近年来，流量工程对QoS (Quality of Service)的保证问题进行了广泛的研究。该方案是一种基于片上立体网络的实验解决方案，其中虚拟链路和虚拟节点由一些pe(处理元素)构成。通过片上立体网络中虚拟数据包的交换行为，得到了真实的流量波动情况。在本文中，作为实现我们最终目标的第一次尝试，我们实现了diorama网络并确定了基本路径计算，这两个函数都是我们算法的基本函数。立体网络流量工程可以实现更复杂的网络设计，如自适应流量均衡或多度量设计。
{"title":"A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2","authors":"Shan Gao, T. Kihara, S. Shimizu, Y. Arakawa, N. Yamanaka, Akifumi Watanabey","doi":"10.1109/HPSR.2009.5307432","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307432","url":null,"abstract":"This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (Quality of Service). The proposal is an experimental solution with the onchip diorama network, where virtual links and virtual nodes are constructed by some PEs (processing elements). We obtain the realistic traffic fluctuation through the behavior of virtual packets exchanged on the on-chip diorama network. In this paper, as first trial to achieve our final goal, we implemented diorama network and confirmed basic path calculation, where both functions are an essential function of our algorithm. The diorama network traffic engineering can realize more sophisticated network design like adaptive traffic balancing or multi-metric design.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115058750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307419
Yeim-Kuan Chang, Fang-Chen Kuo
It is well-known that there are bursty accesses in network traffic. It means a burst of packets with the same meaningful headers are usually received by routers at the same time. With such traffic, routers usually perform the same computations and access the same memory location repeatedly. To utilize this characteristic of network traffic, many cache schemes are proposed to deal with the bursty access patterns. However, in the multi-thread network processor based routers, the existing cache schemes will not suit to the bursty traffic. Since all threads may all deal with the packets with the same headers, if the former threads do not update the cache entries yet, the subsequent threads still have to repeat the computations due to the cache miss. In this paper, we propose a cache scheme called B-cache for the multi-thread network processors. B-cache blocks the subsequent threads from doing the same computations which are being processed by the former thread. By applying B-cache, any packet processing tasks with high locality characteristic, such as IP address lookup, packet classification, and intrusion detection, can avoid the duplicate computations and hence achieve a better packet processing rate. We implement the proposed B-cache scheme on Intel IXP2400 network processor, the experimental results shows that our B-cache scheme can achieves the line speed of Intel IXP2400.
{"title":"Packet processing with blocking for bursty traffic on multi-thread network processor","authors":"Yeim-Kuan Chang, Fang-Chen Kuo","doi":"10.1109/HPSR.2009.5307419","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307419","url":null,"abstract":"It is well-known that there are bursty accesses in network traffic. It means a burst of packets with the same meaningful headers are usually received by routers at the same time. With such traffic, routers usually perform the same computations and access the same memory location repeatedly. To utilize this characteristic of network traffic, many cache schemes are proposed to deal with the bursty access patterns. However, in the multi-thread network processor based routers, the existing cache schemes will not suit to the bursty traffic. Since all threads may all deal with the packets with the same headers, if the former threads do not update the cache entries yet, the subsequent threads still have to repeat the computations due to the cache miss. In this paper, we propose a cache scheme called B-cache for the multi-thread network processors. B-cache blocks the subsequent threads from doing the same computations which are being processed by the former thread. By applying B-cache, any packet processing tasks with high locality characteristic, such as IP address lookup, packet classification, and intrusion detection, can avoid the duplicate computations and hence achieve a better packet processing rate. We implement the proposed B-cache scheme on Intel IXP2400 network processor, the experimental results shows that our B-cache scheme can achieves the line speed of Intel IXP2400.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128525044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307431
C. Meusburger, D. Schupke
Growing traffic loads in communication networks demand for cost-efficient multi-degree switching architectures. Implementing reconfigurable optical add/drop multiplexers (ROADMs) offers cost-efficient and highly flexible solutions in terms of wavelength and direction reconfigurability. First, we give an overview of existing ROADM architectures by introducing a classification matrix. In the second part of the paper, we propose and analyze a concept, which can overcome scalability limitations and decrease the cost of ROADMs connected by parallel fiber pairs. This concept is based on the elimination of switching components, while preserving the most important flexibility advantages of a ROADM.
{"title":"Scalability of ROADMs for multiple parallel fibers","authors":"C. Meusburger, D. Schupke","doi":"10.1109/HPSR.2009.5307431","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307431","url":null,"abstract":"Growing traffic loads in communication networks demand for cost-efficient multi-degree switching architectures. Implementing reconfigurable optical add/drop multiplexers (ROADMs) offers cost-efficient and highly flexible solutions in terms of wavelength and direction reconfigurability. First, we give an overview of existing ROADM architectures by introducing a classification matrix. In the second part of the paper, we propose and analyze a concept, which can overcome scalability limitations and decrease the cost of ROADMs connected by parallel fiber pairs. This concept is based on the elimination of switching components, while preserving the most important flexibility advantages of a ROADM.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131663315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307433
Kazumasa Tokuhashi, Kunitaka Ashizawa, D. Ishii, Y. Arakawa, N. Yamanaka, K. Wakayama
We are proposing a new optical access network architecture using PLZT 10 nsec high-speed optical switches, called Active Optical Network (ActiON). Our architecture can increase four times the number of subscribers as well as double the distance between OLT and ONUs than GE-PON. Moreover, a user can establish secure communication in ActiON. Because ActiON uses not broadcasting system but slot based switching system. ActiON has to overcome a Discovery process issue because an optical switch can not broadcast. In this paper, we propose a new Discovery process technique. Through simulation results and experimental results, we show that our proposed architecture is able to complete Discovery process with accuracy.
{"title":"Secure and scalable optical access network using PLZT high-speed optical switches","authors":"Kazumasa Tokuhashi, Kunitaka Ashizawa, D. Ishii, Y. Arakawa, N. Yamanaka, K. Wakayama","doi":"10.1109/HPSR.2009.5307433","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307433","url":null,"abstract":"We are proposing a new optical access network architecture using PLZT 10 nsec high-speed optical switches, called Active Optical Network (ActiON). Our architecture can increase four times the number of subscribers as well as double the distance between OLT and ONUs than GE-PON. Moreover, a user can establish secure communication in ActiON. Because ActiON uses not broadcasting system but slot based switching system. ActiON has to overcome a Discovery process issue because an optical switch can not broadcast. In this paper, we propose a new Discovery process technique. Through simulation results and experimental results, we show that our proposed architecture is able to complete Discovery process with accuracy.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133544089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307438
Bing Hu, K. Yeung
Scalability is of paramount importance in high-speed switch design. Two limiting factors are the complexity of switch fabric and the need for a sophisticated central scheduler. In this paper, we focus on designing a scalable multicast switch. Given the fact that the majority traffic on the Internet is unicast, a costeffective solution is to adopt a unicast switch fabric for handling both unicast and multicast traffic. Unlike existing approaches, we choose to base our multicast switch design on the load-balanced two-stage switch architecture because it does not require a central scheduler, and its unicast switch fabric only needs to realize N switch configurations. Specifically, we adopt the feedback-based two-stage switch architecture [10], because it elegantly solves the notorious packet mis-sequencing problem, and yet renders an excellent throughput-delay performance. By slightly modifying the operation of the original feedback-based two-stage switch, a simple distributed multicast scheduling algorithm is proposed. Simulation results show that with packet duplication at both input ports and middle-stage ports, the proposed multicast scheduling algorithm significantly cuts down the average packet delay and delay variation among different copies of the same multicast packet.
{"title":"Multicast scheduling in feedback-based two-stage switch","authors":"Bing Hu, K. Yeung","doi":"10.1109/HPSR.2009.5307438","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307438","url":null,"abstract":"Scalability is of paramount importance in high-speed switch design. Two limiting factors are the complexity of switch fabric and the need for a sophisticated central scheduler. In this paper, we focus on designing a scalable multicast switch. Given the fact that the majority traffic on the Internet is unicast, a costeffective solution is to adopt a unicast switch fabric for handling both unicast and multicast traffic. Unlike existing approaches, we choose to base our multicast switch design on the load-balanced two-stage switch architecture because it does not require a central scheduler, and its unicast switch fabric only needs to realize N switch configurations. Specifically, we adopt the feedback-based two-stage switch architecture [10], because it elegantly solves the notorious packet mis-sequencing problem, and yet renders an excellent throughput-delay performance. By slightly modifying the operation of the original feedback-based two-stage switch, a simple distributed multicast scheduling algorithm is proposed. Simulation results show that with packet duplication at both input ports and middle-stage ports, the proposed multicast scheduling algorithm significantly cuts down the average packet delay and delay variation among different copies of the same multicast packet.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134017787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307439
C. Minkenberg, A. Scicchitano, M. Gusat
A significant drive to consolidate data center networks on a single infrastructure is taking place. 10-Gigabit Ethernet is one of the contenders to fulfill the role of universal data center interconnect. One of the key features missing from conventional Ethernet is congestion management; this void is being filled by the standardization work of the IEEE 802.1Qau working group. However, the schemes under consideration react to congestion only at the sources by reducing the transmission rates of “hot” flows, i.e., those detected as contributing to congestion. This approach ignores a crucial aspect of many data center networks, namely, that there typically are multiple paths between any pair of end nodes. Before reducing transmission rates, it would make sense to look for an alternative, uncongested path first. Here, we propose an adaptive routing scheme that builds—in a fully transparent way—on top of the existing 802.1Qau schemes, by snooping the congestion notification frames to modify the routing behavior of the switching nodes. We demonstrate how this can lead to significant performance improvements by taking full advantage of path diversity.
{"title":"Adaptive routing for Convergence Enhanced Ethernet","authors":"C. Minkenberg, A. Scicchitano, M. Gusat","doi":"10.1109/HPSR.2009.5307439","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307439","url":null,"abstract":"A significant drive to consolidate data center networks on a single infrastructure is taking place. 10-Gigabit Ethernet is one of the contenders to fulfill the role of universal data center interconnect. One of the key features missing from conventional Ethernet is congestion management; this void is being filled by the standardization work of the IEEE 802.1Qau working group. However, the schemes under consideration react to congestion only at the sources by reducing the transmission rates of “hot” flows, i.e., those detected as contributing to congestion. This approach ignores a crucial aspect of many data center networks, namely, that there typically are multiple paths between any pair of end nodes. Before reducing transmission rates, it would make sense to look for an alternative, uncongested path first. Here, we propose an adaptive routing scheme that builds—in a fully transparent way—on top of the existing 802.1Qau schemes, by snooping the congestion notification frames to modify the routing behavior of the switching nodes. We demonstrate how this can lead to significant performance improvements by taking full advantage of path diversity.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130490298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307424
Zhanliang Liu, Huan Wang, Wu Hu, Yang Hong, O. Yang, Y. Shu
Adaptive PI Rate Control Protocol (API-RCP) has been proposed as an explicit congestion control mechanism [1]. In this paper, a Linux-based testbed is created to validate the features and performance of API-RCP. Various issues on implementing API-RCP in Linux kernel are addressed. There are two outcomes of our experimental results: a) Confirm that in practice API-RCP is as effective as the theory asserts in achieving a high and smooth sending rate, a small and smooth round trip time (RTT), an almost full link utilization and zero packet drop, and b) Demonstrate that API-RCP exhibits good robustness to varying network environment with changing flows or network delays. All these support that API-RCP is a very viable candidate in the real network implementations.
{"title":"An implementation and experimental study of the Adaptive PI Rate Control Protocol","authors":"Zhanliang Liu, Huan Wang, Wu Hu, Yang Hong, O. Yang, Y. Shu","doi":"10.1109/HPSR.2009.5307424","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307424","url":null,"abstract":"Adaptive PI Rate Control Protocol (API-RCP) has been proposed as an explicit congestion control mechanism [1]. In this paper, a Linux-based testbed is created to validate the features and performance of API-RCP. Various issues on implementing API-RCP in Linux kernel are addressed. There are two outcomes of our experimental results: a) Confirm that in practice API-RCP is as effective as the theory asserts in achieving a high and smooth sending rate, a small and smooth round trip time (RTT), an almost full link utilization and zero packet drop, and b) Demonstrate that API-RCP exhibits good robustness to varying network environment with changing flows or network delays. All these support that API-RCP is a very viable candidate in the real network implementations.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-22DOI: 10.1109/HPSR.2009.5307435
Z. Čiča, A. Smiljanic
Lookup function in the IP routers has always been a topic of a great interest since it represents a potential bottleneck in improving Internet router's capacity. IP lookup stands for the search of the longest matching prefix in the lookup table for the given destination IP address. The lookup process must be fast in order to support increasing port bit-rates and the number of IP addresses. The lookup table updates must be also performed fast because they happen frequently. In this paper, we propose a new algorithm based on the parallel search implemented on the FPGA chip that finds the next hop information in the external memory. The lookup algorithm must support both the existing IPv4 protocol, as well as the future IPv6 protocol. We analyze the performance of the designed algorithm, and compare it with the existing lookup algorithms. Our proposed algorithm allows a fast search because it is parallelized within the FPGA chip. Also, it utilizes the memory more efficiently than other algorithms because it does not use the resources for the empty subtrees. The update process that the proposed algorithm performs is as fast as the search process. The proposed algorithm will be implemented and analyzed for both IPv4 and IPv6. It will be shown that it supports IPv6 effectively.
{"title":"Frugal IP lookup based on a parallel search","authors":"Z. Čiča, A. Smiljanic","doi":"10.1109/HPSR.2009.5307435","DOIUrl":"https://doi.org/10.1109/HPSR.2009.5307435","url":null,"abstract":"Lookup function in the IP routers has always been a topic of a great interest since it represents a potential bottleneck in improving Internet router's capacity. IP lookup stands for the search of the longest matching prefix in the lookup table for the given destination IP address. The lookup process must be fast in order to support increasing port bit-rates and the number of IP addresses. The lookup table updates must be also performed fast because they happen frequently. In this paper, we propose a new algorithm based on the parallel search implemented on the FPGA chip that finds the next hop information in the external memory. The lookup algorithm must support both the existing IPv4 protocol, as well as the future IPv6 protocol. We analyze the performance of the designed algorithm, and compare it with the existing lookup algorithms. Our proposed algorithm allows a fast search because it is parallelized within the FPGA chip. Also, it utilizes the memory more efficiently than other algorithms because it does not use the resources for the empty subtrees. The update process that the proposed algorithm performs is as fast as the search process. The proposed algorithm will be implemented and analyzed for both IPv4 and IPv6. It will be shown that it supports IPv6 effectively.","PeriodicalId":251545,"journal":{"name":"2009 International Conference on High Performance Switching and Routing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123559192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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