Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625544
N. Doan, F. Robert, Y. D. Smet, D. Milojevic
Recently, the academic and industrial communities have proposed new technologies in order to overcome the physical limitations of the silicon, and among them 3D-Stacked Integrated Circuits (3D-SIC). Manufacturing of 3D-SICs consists in piling up conventional CMOS ICs and creating vertical interconnections between them. This offers new perspectives and levels of performance but the question of efficiently designing them arises since the solution space increases significantly. This paper presents a first approach based on a multi-criteria method in order to be able to efficiently design 3D-SIC. The aim of this work is to quickly explore the design space while considering the numerous criteria involved. This work is a first approach that shows a new design method based on the use of Multi- Criteria Decision Aid (MCDA) tools for efficient 3D-SIC design. The problem considered in this first approach is a global 3D-floorplanning. This work has shown that using MCDA tools can provide objective information that would not be available with the current conventional design methods. Those information provides deep analyses which could answer some of the questions a designer may have about the design space of a circuit. We believe that, with these promising results, this MCDA-based method will allow designers to overcome the growing complexity of designing 3D-SICs.
{"title":"MCDA-based methodology for efficient 3D-design space exploration and decision","authors":"N. Doan, F. Robert, Y. D. Smet, D. Milojevic","doi":"10.1109/ISSOC.2010.5625544","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625544","url":null,"abstract":"Recently, the academic and industrial communities have proposed new technologies in order to overcome the physical limitations of the silicon, and among them 3D-Stacked Integrated Circuits (3D-SIC). Manufacturing of 3D-SICs consists in piling up conventional CMOS ICs and creating vertical interconnections between them. This offers new perspectives and levels of performance but the question of efficiently designing them arises since the solution space increases significantly. This paper presents a first approach based on a multi-criteria method in order to be able to efficiently design 3D-SIC. The aim of this work is to quickly explore the design space while considering the numerous criteria involved. This work is a first approach that shows a new design method based on the use of Multi- Criteria Decision Aid (MCDA) tools for efficient 3D-SIC design. The problem considered in this first approach is a global 3D-floorplanning. This work has shown that using MCDA tools can provide objective information that would not be available with the current conventional design methods. Those information provides deep analyses which could answer some of the questions a designer may have about the design space of a circuit. We believe that, with these promising results, this MCDA-based method will allow designers to overcome the growing complexity of designing 3D-SICs.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127949465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.4018/jertcs.2011070102
S. Hollis, C. Jackson
We introduce the Skip-link architecture that dynamically reconfigures Network-on-Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in the literature such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. Our architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. Our technique does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. We evaluate the performance using a cycle-accurate simulation with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating hop count and energy reductions of around 10%.
{"title":"Skip-links: A dynamically reconfiguring topology for energy-efficient NoCs","authors":"S. Hollis, C. Jackson","doi":"10.4018/jertcs.2011070102","DOIUrl":"https://doi.org/10.4018/jertcs.2011070102","url":null,"abstract":"We introduce the Skip-link architecture that dynamically reconfigures Network-on-Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in the literature such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. Our architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. Our technique does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. We evaluate the performance using a cycle-accurate simulation with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating hop count and energy reductions of around 10%.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115088119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625555
T. Aarnio, C. Brunelli, T. Viitanen
We propose a novel hardware design for decoding compressed floating-point textures in a graphics processing unit (GPU). Our decoder is based on the NXR texture format, which provides lossy, fixed-rate 6∶1 compression for floating-point textures. Our design exploits the constraints of the compressed pixel blocks to produce the correct output using only fixed-point arithmetic. This results in significantly lower silicon area occupation compared to pre-existing floating-point texture decoders.
{"title":"Efficient floating-point texture decompression","authors":"T. Aarnio, C. Brunelli, T. Viitanen","doi":"10.1109/ISSOC.2010.5625555","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625555","url":null,"abstract":"We propose a novel hardware design for decoding compressed floating-point textures in a graphics processing unit (GPU). Our decoder is based on the NXR texture format, which provides lossy, fixed-rate 6∶1 compression for floating-point textures. Our design exploits the constraints of the compressed pixel blocks to produce the correct output using only fixed-point arithmetic. This results in significantly lower silicon area occupation compared to pre-existing floating-point texture decoders.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"16 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133204324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-29DOI: 10.1109/ISSOC.2010.5625564
Timon D. ter Braak, S. T. Burgess, H. Hurskainen, H. Kerkhoff, B. Vermeulen, Xiao Zhang
This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line structural self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation.
{"title":"On-line dependability enhancement of multiprocessor SoCs by resource management","authors":"Timon D. ter Braak, S. T. Burgess, H. Hurskainen, H. Kerkhoff, B. Vermeulen, Xiao Zhang","doi":"10.1109/ISSOC.2010.5625564","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625564","url":null,"abstract":"This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line structural self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-01DOI: 10.1109/ISSOC.2010.5625546
Matthias Korb, T. Noll
System specification of SoCs needs to be supported by quantitative cost models to avoid wrong decisions in this early design phase. For less complex logic structures like for example FIR filters such generic cost models can be derived easily because they base on a simple gate count. For LDPC decoders the influence of the global interconnect between the two basic components of such a decoder complicates the derivation of general cost models. This might be the reason why no accurate cost models are known from literature yet. In this paper generic silicon area, iteration period, and energy cost models of high-throughput LDPC decoders are derived. Those models do not only allow for a decoding-performance vs. hardware-cost trade-off analysis during system specification but can also be used later on to choose a suitable architecture for a certain specification. Finally these models can be used for a fair benchmarking of the implemented decoder.
{"title":"LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates","authors":"Matthias Korb, T. Noll","doi":"10.1109/ISSOC.2010.5625546","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625546","url":null,"abstract":"System specification of SoCs needs to be supported by quantitative cost models to avoid wrong decisions in this early design phase. For less complex logic structures like for example FIR filters such generic cost models can be derived easily because they base on a simple gate count. For LDPC decoders the influence of the global interconnect between the two basic components of such a decoder complicates the derivation of general cost models. This might be the reason why no accurate cost models are known from literature yet. In this paper generic silicon area, iteration period, and energy cost models of high-throughput LDPC decoders are derived. Those models do not only allow for a decoding-performance vs. hardware-cost trade-off analysis during system specification but can also be used later on to choose a suitable architecture for a certain specification. Finally these models can be used for a fair benchmarking of the implemented decoder.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134381664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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