Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625557
Alexander Klimm, M. Haas, O. Sander, J. Becker
An integrated cryptographic processor for public key cryptography for embedded systems is proposed in this contribution. The architecture is designed for computational intensive applications based on hyperelliptic curve cryptography (HECC) in the automotive domain. Authentication protocols based on HECC can be adapted for access control systems and demobilizer applications in today's cars. They can raise the security level of these systems, but ask for more computation power than is available in current automotive platforms. Good programmability of the system in high level languages such as C eases the integration of the proposed platform into existing systems and development flows in the automotive domain. In order to include such a level of abstraction a software programmable application specific processor was developed. This processor allows to hide the complex hardware of HECC and avoids a long term hardware development in case of a re-design. The benefit of a software based system combined with a specialized hardware is provided with the described approach. The presented work therefore follows the novel methodology of hardware software codesign where the benefits of both development methodologies are combined in the final system. Experiments show that a substantial gain in computation speed can be achieved while keeping the gate count low.
{"title":"A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography","authors":"Alexander Klimm, M. Haas, O. Sander, J. Becker","doi":"10.1109/ISSOC.2010.5625557","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625557","url":null,"abstract":"An integrated cryptographic processor for public key cryptography for embedded systems is proposed in this contribution. The architecture is designed for computational intensive applications based on hyperelliptic curve cryptography (HECC) in the automotive domain. Authentication protocols based on HECC can be adapted for access control systems and demobilizer applications in today's cars. They can raise the security level of these systems, but ask for more computation power than is available in current automotive platforms. Good programmability of the system in high level languages such as C eases the integration of the proposed platform into existing systems and development flows in the automotive domain. In order to include such a level of abstraction a software programmable application specific processor was developed. This processor allows to hide the complex hardware of HECC and avoids a long term hardware development in case of a re-design. The benefit of a software based system combined with a specialized hardware is provided with the described approach. The presented work therefore follows the novel methodology of hardware software codesign where the benefits of both development methodologies are combined in the final system. Experiments show that a substantial gain in computation speed can be achieved while keeping the gate count low.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625558
A. Abdallah, A. Gamatie, J. Dekeyser
This paper presents the design and analysis of a multimedia system-on-chip consisting of the H.264 encoder implemented on a multiprocessor architecture. A model-driven approach is adopted by using the standard MARTE profile of UML. An abstract clock analysis is applied to deal with the correctness of the system temporal properties and to find the most suitable execution platform configurations regarding the energy consumption. We claim that our approach allows for an early design space exploration, which is crucial when implementing modern complex systems.
{"title":"Correct and energy-efficient design of SoCs: The H.264 encoder case study","authors":"A. Abdallah, A. Gamatie, J. Dekeyser","doi":"10.1109/ISSOC.2010.5625558","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625558","url":null,"abstract":"This paper presents the design and analysis of a multimedia system-on-chip consisting of the H.264 encoder implemented on a multiprocessor architecture. A model-driven approach is adopted by using the standard MARTE profile of UML. An abstract clock analysis is applied to deal with the correctness of the system temporal properties and to find the most suitable execution platform configurations regarding the energy consumption. We claim that our approach allows for an early design space exploration, which is crucial when implementing modern complex systems.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114480234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625562
Roberto Airoldi, F. Garzia, Omer Anjum, J. Nurmi
This paper presents a homogeneous Multi-Processor System-on-Chip (MPSoC) as baseband signal processing engine for software defined radio applications. The implementation and parallelisation of a generic OFDM system is presented taking as study case the physical layer of the IEEE 802.11a standard. The MPSoC is composed of nine computational nodes connected in a mesh topology through a hierarchical network-on-chip. Each node hosts a COFFEE RISC processor as processing element. The architecture was prototyped on an ALTERA STRATIX IV FPGA working at a maximum frequency of 180 MHz.
本文提出了一种同构多处理器片上系统(MPSoC)作为软件无线电应用的基带信号处理引擎。以IEEE 802.11a标准的物理层为研究对象，提出了一种通用OFDM系统的并行化实现方法。MPSoC由九个计算节点组成，通过层次化的片上网络以网状拓扑连接。每个节点承载一个COFFEE RISC处理器作为处理单元。该架构在ALTERA STRATIX IV FPGA上进行原型设计，最大工作频率为180 MHz。
{"title":"Homogeneous MPSoC as baseband signal processing engine for OFDM systems","authors":"Roberto Airoldi, F. Garzia, Omer Anjum, J. Nurmi","doi":"10.1109/ISSOC.2010.5625562","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625562","url":null,"abstract":"This paper presents a homogeneous Multi-Processor System-on-Chip (MPSoC) as baseband signal processing engine for software defined radio applications. The implementation and parallelisation of a generic OFDM system is presented taking as study case the physical layer of the IEEE 802.11a standard. The MPSoC is composed of nine computational nodes connected in a mesh topology through a hierarchical network-on-chip. Each node hosts a COFFEE RISC processor as processing element. The architecture was prototyped on an ALTERA STRATIX IV FPGA working at a maximum frequency of 180 MHz.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128450233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625548
Joonas Tyystjärvi, T. Säntti, J. Plosila
The REALJava virtual machine consists of a software partition running on a general-purpose CPU and a hardware partition containing one or more Java co-processor units. The co-processor units execute most of the bytecode, while the software partition handles complex instructions and tasks such as class loading, input and output and memory management. The software partition and the co-processors communicate using a general communication channel such as a bus. By far the most common instructions executed in the software partition are heap accesses. Because executing instructions on software is relatively slow, code-improving transformations which reduce the number of interrupts generated and the amount of communication can have a large impact on performance. An improvement on an existing technique called supersequence transformation is presented which makes the technique more general and reduces the amount of communication required between the partitions and the number of interrupts generated. The improved technique is shown to improve performance over the original in many programs.
{"title":"Heap access optimizations for a hardware-accelerated Java virtual machine","authors":"Joonas Tyystjärvi, T. Säntti, J. Plosila","doi":"10.1109/ISSOC.2010.5625548","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625548","url":null,"abstract":"The REALJava virtual machine consists of a software partition running on a general-purpose CPU and a hardware partition containing one or more Java co-processor units. The co-processor units execute most of the bytecode, while the software partition handles complex instructions and tasks such as class loading, input and output and memory management. The software partition and the co-processors communicate using a general communication channel such as a bus. By far the most common instructions executed in the software partition are heap accesses. Because executing instructions on software is relatively slow, code-improving transformations which reduce the number of interrupts generated and the amount of communication can have a large impact on performance. An improvement on an existing technique called supersequence transformation is presented which makes the technique more general and reduces the amount of communication required between the partitions and the number of interrupts generated. The improved technique is shown to improve performance over the original in many programs.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114864811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625533
S. Chakraborty
Control applications are now increasingly mapped onto multiprocessor architectures, a familiar example being automotive platforms which now consist of more than 80 electronic control units (ECUs). Such control systems typically consist of several control loops, with different parts of each control application being mapped onto different processors that communicate over one or more communication buses. In such setups, the system architecture and scheduling policies have a significant impact on control performance. In this talk we will discuss both, platform architecture, as well as software design techniques for such setups, in order to satisfy real-time and control performance constraints.
{"title":"Multiprocessor system and software design for distributed control applications","authors":"S. Chakraborty","doi":"10.1109/ISSOC.2010.5625533","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625533","url":null,"abstract":"Control applications are now increasingly mapped onto multiprocessor architectures, a familiar example being automotive platforms which now consist of more than 80 electronic control units (ECUs). Such control systems typically consist of several control loops, with different parts of each control application being mapped onto different processors that communicate over one or more communication buses. In such setups, the system architecture and scheduling policies have a significant impact on control performance. In this talk we will discuss both, platform architecture, as well as software design techniques for such setups, in order to satisfy real-time and control performance constraints.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132967945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625536
V. Guzma, Teemu Pitkänen, J. Takala
Use of Instruction Buffers (also named Repeat Buffers), and caches is common way to avoid memory speed bottleneck in presence of memory hierarchies. Once the instruction resides in a cache or a buffer, repeated execution of the same instruction does not require separate memory access and possible cache miss. Use of the instruction buffers offer also an advantage when low energy consumption is an issue. Reading instruction from the buffer requires order of magnitude less energy then fetch from instruction memory. Keeping memories in the deselect mode and fetching data from the buffer takes roughly half of the power compared to the reading from the memory. In this work, we analyze effects of adding instruction buffer to an existing ASIP architecture. We analyze already generated code of an application, to find the often executed loops, and augment instructions with instruction buffer control information. We show, that for many of embedded applications, storing kernels of execution in the instruction buffer saves between 60 to 87% of instruction memory, even with most trivial loops. This savings can translate to up to 47% reduction of memory energy.
{"title":"Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis","authors":"V. Guzma, Teemu Pitkänen, J. Takala","doi":"10.1109/ISSOC.2010.5625536","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625536","url":null,"abstract":"Use of Instruction Buffers (also named Repeat Buffers), and caches is common way to avoid memory speed bottleneck in presence of memory hierarchies. Once the instruction resides in a cache or a buffer, repeated execution of the same instruction does not require separate memory access and possible cache miss. Use of the instruction buffers offer also an advantage when low energy consumption is an issue. Reading instruction from the buffer requires order of magnitude less energy then fetch from instruction memory. Keeping memories in the deselect mode and fetching data from the buffer takes roughly half of the power compared to the reading from the memory. In this work, we analyze effects of adding instruction buffer to an existing ASIP architecture. We analyze already generated code of an application, to find the often executed loops, and augment instructions with instruction buffer control information. We show, that for many of embedded applications, storing kernels of execution in the instruction buffer saves between 60 to 87% of instruction memory, even with most trivial loops. This savings can translate to up to 47% reduction of memory energy.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125365586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625534
S. Höppner, D. Walter, H. Eisenreich, R. Schüffny
This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations can significantly reduce yield at high data rates and high bus widths. An on-chip delay calibration architecture for individual calibration of rise and fall delay times is proposed and analyzed on system level using Monte Carlo simulations. A sizing strategy for compensation delay elements is derived for yield maximization with low effort in terms of chip area and energy consumption.
{"title":"Efficient compensation of delay variations in high-speed network-on-chip data links","authors":"S. Höppner, D. Walter, H. Eisenreich, R. Schüffny","doi":"10.1109/ISSOC.2010.5625534","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625534","url":null,"abstract":"This paper analyzes high-speed source-synchronous network-on-chip data links in terms of yield loss due to delay variations. We show that statistical process variations can significantly reduce yield at high data rates and high bus widths. An on-chip delay calibration architecture for individual calibration of rise and fall delay times is proposed and analyzed on system level using Monte Carlo simulations. A sizing strategy for compensation delay elements is derived for yield maximization with low effort in terms of chip area and energy consumption.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625539
Alessandro Strano, Carles Hernández, F. Silla, D. Bertozzi
Synchronization interfaces in a network-on-chip (NoC) are becoming vulnerable points that need to be safeguarded against link delay variations and signal misalignments. This paper addresses the challenge of designing a process variation and layout mismatch tolerant link for GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. The paper proves correct operation of the GALS link augmented with the variation detector and compares its reliability with that of a detector-less link, beyond proving robustness with respect to the delay variability affecting the detector itself.
{"title":"Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip","authors":"Alessandro Strano, Carles Hernández, F. Silla, D. Bertozzi","doi":"10.1109/ISSOC.2010.5625539","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625539","url":null,"abstract":"Synchronization interfaces in a network-on-chip (NoC) are becoming vulnerable points that need to be safeguarded against link delay variations and signal misalignments. This paper addresses the challenge of designing a process variation and layout mismatch tolerant link for GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. The paper proves correct operation of the GALS link augmented with the variation detector and compares its reliability with that of a detector-less link, beyond proving robustness with respect to the delay variability affecting the detector itself.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128655534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625540
Spencer S. Kellis, N. Gaskin, Bennion Redd, E. Marsman, Richard B. Brown
On-chip clock generation is an attractive alternative to external quartz oscillators for low-power sensing systems. LC and ring oscillators typically use less power, and can start and stop much faster than traditional quartz oscillators, allowing systems to spend more time in low-power sleep states. A hybrid on-chip clocking scheme is evaluated in which a ring oscillator is used as the reference clock for digital processing, and an LC oscillator is used when a more stable, accurate reference is needed for digital communication. Simulations show that the fast wakeup capabilities of the hybrid clock system lead to as much as 80% reduced power in interrupt-driven applications compared to a system using a crystal reference clock source. The on-chip clock generators of the WIMS series of microsystems are described to demonstrate the concept of the hybrid clock scheme.
{"title":"Hybrid on-chip clocking for sensor nodes","authors":"Spencer S. Kellis, N. Gaskin, Bennion Redd, E. Marsman, Richard B. Brown","doi":"10.1109/ISSOC.2010.5625540","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625540","url":null,"abstract":"On-chip clock generation is an attractive alternative to external quartz oscillators for low-power sensing systems. LC and ring oscillators typically use less power, and can start and stop much faster than traditional quartz oscillators, allowing systems to spend more time in low-power sleep states. A hybrid on-chip clocking scheme is evaluated in which a ring oscillator is used as the reference clock for digital processing, and an LC oscillator is used when a more stable, accurate reference is needed for digital communication. Simulations show that the fast wakeup capabilities of the hybrid clock system lead to as much as 80% reduced power in interrupt-driven applications compared to a system using a crystal reference clock source. The on-chip clock generators of the WIMS series of microsystems are described to demonstrate the concept of the hybrid clock scheme.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122517236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-09DOI: 10.1109/ISSOC.2010.5625550
Lasse Määttä, J. Suhonen, Teemu Laukkarinen, T. Hämäläinen, Marko Hännikäinen
A Wireless Sensor Network (WSN) consists of programmable, low-cost and resource-constrained nodes. Adding new features or error fixes requires reprogramming nodes. Manually reprogramming hundreds or thousands of nodes is impractical as it takes significant effort and time. Therefore, WSNs require a mechanism for updating the nodes program image, which contains the applications and protocols running on each node. Current protocols for updating program images rely on a large external memory that is used to temporary store program images. In this paper we present the design, implementation and experimental measurements of a lightweight and reliable Program Image Dissemination Protocol (PIDP) for autonomous adhoc multihop WSNs. PIDP requires no external memory storage, is independent of the WSN stack, offers a low overhead protocol for transferring program images, and can reprogram the whole WSN stack. An update procedure with PIDP in one part of the network does not interfere with the WSN elsewhere. PIDP was implemented on a node platform with an 8-bit 2 MIPS Microchip PIC18LF8722 microcontroller and a 2.4 GHz Nordic Semiconductors nRF24L01 radio. PIDP requires less than 7 kilobytes of program memory and from 22 to 815 bytes of data memory. In experiments PIDP reprogrammed a campus WSN, which is a running deployment of 178 nodes, in 5 hours.
{"title":"Program image dissemination protocol for low-energy multihop wireless sensor networks","authors":"Lasse Määttä, J. Suhonen, Teemu Laukkarinen, T. Hämäläinen, Marko Hännikäinen","doi":"10.1109/ISSOC.2010.5625550","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625550","url":null,"abstract":"A Wireless Sensor Network (WSN) consists of programmable, low-cost and resource-constrained nodes. Adding new features or error fixes requires reprogramming nodes. Manually reprogramming hundreds or thousands of nodes is impractical as it takes significant effort and time. Therefore, WSNs require a mechanism for updating the nodes program image, which contains the applications and protocols running on each node. Current protocols for updating program images rely on a large external memory that is used to temporary store program images. In this paper we present the design, implementation and experimental measurements of a lightweight and reliable Program Image Dissemination Protocol (PIDP) for autonomous adhoc multihop WSNs. PIDP requires no external memory storage, is independent of the WSN stack, offers a low overhead protocol for transferring program images, and can reprogram the whole WSN stack. An update procedure with PIDP in one part of the network does not interfere with the WSN elsewhere. PIDP was implemented on a node platform with an 8-bit 2 MIPS Microchip PIC18LF8722 microcontroller and a 2.4 GHz Nordic Semiconductors nRF24L01 radio. PIDP requires less than 7 kilobytes of program memory and from 22 to 815 bytes of data memory. In experiments PIDP reprogrammed a campus WSN, which is a running deployment of 178 nodes, in 5 hours.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131023857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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