Pub Date : 2011-06-05DOI: 10.1109/ESLSYN.2011.5952285
Yuexi Ma, Huafeng Yu, T. Gautier, J. Talpin, L. Besnard, P. Le Guernic
The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and performing fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in this paper: use the high-level modeling, domain-specific, language AADL for system-level co-design; use the formal framework Polychrony, based on the synchronous language Signal, for analysis, validation and synthesis. According to SIGNAL's polychronous model of computation, we propose a model for AADL, which takes both software, hardware and allocation into account. This model enables an early phase timing analysis and synthesis via tools associated with Polychrony.
{"title":"System synthesis from AADL using Polychrony","authors":"Yuexi Ma, Huafeng Yu, T. Gautier, J. Talpin, L. Besnard, P. Le Guernic","doi":"10.1109/ESLSYN.2011.5952285","DOIUrl":"https://doi.org/10.1109/ESLSYN.2011.5952285","url":null,"abstract":"The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and performing fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in this paper: use the high-level modeling, domain-specific, language AADL for system-level co-design; use the formal framework Polychrony, based on the synchronous language Signal, for analysis, validation and synthesis. According to SIGNAL's polychronous model of computation, we propose a model for AADL, which takes both software, hardware and allocation into account. This model enables an early phase timing analysis and synthesis via tools associated with Polychrony.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129072228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/ESLSYN.2011.5952283
H. Manteuffel, C. Bassoy, F. Mayer-Lindenberg
Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%.
{"title":"FPGA-specific optimizations by partial function evaluation","authors":"H. Manteuffel, C. Bassoy, F. Mayer-Lindenberg","doi":"10.1109/ESLSYN.2011.5952283","DOIUrl":"https://doi.org/10.1109/ESLSYN.2011.5952283","url":null,"abstract":"Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122616956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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