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Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02最新文献

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The Pensieve project: a compiler infrastructure for memory models Pensieve项目:内存模型的编译器基础结构
D. Wong, Zehra Sura, D. Padua, Xing Fang, Jaejin Lee, S. Midkiff
The design of memory consistency models for both hardware and software is a difficult task. It is particularly difficult for a programming language because the target audience is much wider than the target audience for a machine language, making usability a more important criterion. Adding to this problem is the fact that the programming language community has little experience with designing programming language consistency models, and therefore each new attempt is very much a voyage into uncharted territory. A concrete example of the difficulties of the task is the current Java memory model. Although designed to be easy to use by Java programmers, it is poorly understood, and at least one common idiom (the "double-check idiom") to exploit the model is unsafe. In this paper, we describe the design of an optimizing Java compiler that accepts, as either input or as an interface implementation, a consistency model for the code to be compiled. The compiler uses escape analysis, D. Shasha and M. Snir's (1988) delay set analysis, and our own CSSA (concurrent static single assignment) program representation to normalize the effects of different consistency models on optimizations and analysis. The compiler is intended to serve as a testbed to prototype new memory models and to measure the differences between different memory models in terms of program performance.
硬件和软件内存一致性模型的设计是一项艰巨的任务。这对于编程语言来说尤其困难,因为目标受众比机器语言的目标受众要广泛得多,这使得可用性成为更重要的标准。使这个问题更加严重的是,编程语言社区在设计编程语言一致性模型方面几乎没有经验,因此每次新的尝试都是进入未知领域的一次航行。当前的Java内存模型是该任务难点的一个具体例子。尽管被设计为易于Java程序员使用,但它很难被理解,并且至少有一种利用该模型的常用习惯用法(“双重检查习惯用法”)是不安全的。在本文中,我们描述了一个优化Java编译器的设计,该编译器接受要编译的代码的一致性模型,作为输入或接口实现。编译器使用转义分析、D. Shasha和M. Snir(1988)的延迟集分析和我们自己的CSSA(并发静态单赋值)程序表示来规范不同一致性模型对优化和分析的影响。编译器的目的是作为一个测试平台,以原型化新的内存模型,并衡量不同内存模型之间在程序性能方面的差异。
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Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02
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