Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004290
Tong Chen, Jin Lin, W. Hsu, P. Yew
Many applications written in C allocate memory blocks for their major data structures from the heap space at run time. The analysis of heap-oriented pointers in such programs is critical for compilers to generate high-performance code. However, most previous research on pointer analysis mostly focuses on pointers pointing to global or local variables. In this paper, we study points-to analysis of heap-oriented pointers using profiling information. An instrumentation tool and a set of library routines are developed to measure points-to sets of memory references at run time. Different naming methods for heap-oriented pointers are studied. We found that it is very important to adopt appropriate naming methods to recognize wrapper functions for memory allocation and memory management functions defined by users. Based on these naming methods, the approaches in pointer analysis, such as flow sensitivity and context sensitivity, are examined with the run-time tool. The program characteristics are observed at run time to evaluate what kind of compiler analysis is needed. Experiments are conducted on SPEC CPU2000 integer benchmarks. We found that flow sensitivity and context sensitivity have little impact on the analysis of heap-oriented pointers.
{"title":"On the impact of naming methods for heap-oriented pointers in C programs","authors":"Tong Chen, Jin Lin, W. Hsu, P. Yew","doi":"10.1109/ISPAN.2002.1004290","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004290","url":null,"abstract":"Many applications written in C allocate memory blocks for their major data structures from the heap space at run time. The analysis of heap-oriented pointers in such programs is critical for compilers to generate high-performance code. However, most previous research on pointer analysis mostly focuses on pointers pointing to global or local variables. In this paper, we study points-to analysis of heap-oriented pointers using profiling information. An instrumentation tool and a set of library routines are developed to measure points-to sets of memory references at run time. Different naming methods for heap-oriented pointers are studied. We found that it is very important to adopt appropriate naming methods to recognize wrapper functions for memory allocation and memory management functions defined by users. Based on these naming methods, the approaches in pointer analysis, such as flow sensitivity and context sensitivity, are examined with the run-time tool. The program characteristics are observed at run time to evaluate what kind of compiler analysis is needed. Experiments are conducted on SPEC CPU2000 integer benchmarks. We found that flow sensitivity and context sensitivity have little impact on the analysis of heap-oriented pointers.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122077205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004275
J. Bordim, K. Nakano, Hong Shen
A wireless sensor network is a distributed system which consists of a base station and a number of wireless sensors nodes endowed with radio transceivers. The main contribution of this work is to present a sorting protocol for multi-hop wireless sensor networks. Our protocol sorts n elements which are initially loaded in n sensor nodes that are organized in a two-dimensional plane of size /spl radic/n/spl times//spl radic/n. The sorting protocol proposed here sorts the n elements in O(r/spl radic/n) time slots when /spl radic/n > r, where r is the transmission range of the sensor nodes.
{"title":"Sorting on single-channel wireless sensor networks","authors":"J. Bordim, K. Nakano, Hong Shen","doi":"10.1109/ISPAN.2002.1004275","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004275","url":null,"abstract":"A wireless sensor network is a distributed system which consists of a base station and a number of wireless sensors nodes endowed with radio transceivers. The main contribution of this work is to present a sorting protocol for multi-hop wireless sensor networks. Our protocol sorts n elements which are initially loaded in n sensor nodes that are organized in a two-dimensional plane of size /spl radic/n/spl times//spl radic/n. The sorting protocol proposed here sorts the n elements in O(r/spl radic/n) time slots when /spl radic/n > r, where r is the transmission range of the sensor nodes.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127630244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004281
A. Goscinski, P. Jeffers, J. Silcock
In order to schedule parallel processes on available computers there is a need to collect information about different cluster resources. Currently, global scheduling of parallel processes of applications takes into consideration mainly processor load and only in a small number of projects memory utilization. Communication costs, which are high in clusters, are practically neglected. The aim of this paper is to report on our study into cluster parameter measurements, in particular those, which characterize communication costs, the development of the resource discovery server and its initial testing through the study of the influence of communication costs on parallel application performance.
{"title":"Data collection for global scheduling in the GENESIS system","authors":"A. Goscinski, P. Jeffers, J. Silcock","doi":"10.1109/ISPAN.2002.1004281","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004281","url":null,"abstract":"In order to schedule parallel processes on available computers there is a need to collect information about different cluster resources. Currently, global scheduling of parallel processes of applications takes into consideration mainly processor load and only in a small number of projects memory utilization. Communication costs, which are high in clusters, are practically neglected. The aim of this paper is to report on our study into cluster parameter measurements, in particular those, which characterize communication costs, the development of the resource discovery server and its initial testing through the study of the influence of communication costs on parallel application performance.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004301
L. Tan, D. Taniar, K. Smith‐Miles
One problem of propagating the globally fittest individual via neighbourhood evolution in both the island model and the cellular model of existing parallel genetic algorithms (PGAs) is that the migration of the globally best individual is delayed to non-adjacent processors. This may cause an inferior search in those sub-populations. The propagation delay of the globally best individual is proportional to the network distance between two processors. Delayed migration of the best individual in PGAs is an essential deviation from the sequential version of the genetic algorithm, in which the best individuals are always used to compete with other individuals. To solve this problem, this paper proposes an extended version of the island PGA called the Virtual Community PGA (VC-PGA). The VC-PGA is applied in a case study of optimizing the parameters of a backpropagation neural network classifier.
{"title":"A new parallel genetic algorithm","authors":"L. Tan, D. Taniar, K. Smith‐Miles","doi":"10.1109/ISPAN.2002.1004301","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004301","url":null,"abstract":"One problem of propagating the globally fittest individual via neighbourhood evolution in both the island model and the cellular model of existing parallel genetic algorithms (PGAs) is that the migration of the globally best individual is delayed to non-adjacent processors. This may cause an inferior search in those sub-populations. The propagation delay of the globally best individual is proportional to the network distance between two processors. Delayed migration of the best individual in PGAs is an essential deviation from the sequential version of the genetic algorithm, in which the best individuals are always used to compete with other individuals. To solve this problem, this paper proposes an extended version of the island PGA called the Virtual Community PGA (VC-PGA). The VC-PGA is applied in a case study of optimizing the parameters of a backpropagation neural network classifier.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133951842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004261
P. Cappello, Ö. Eğecioğlu
In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequence of dags and linear schedules parameterized by n, compute a lower bound on the number of processors required by the schedule as a function of n. This problem is formulated so that the number of tasks that are scheduled for execution during any fixed time step is the number of non-negative integer solutions d/sub n/ to a set of parametric linear Diophantine equations. Generating function methods are then used for constructing a formula for the numbers dn. We implemented this algorithm as a Mathematica program. This paper is an overview of the techniques involved and their applications to well-known schedules for Matrix-Vector Product, Triangular Matrix Product, and Gaussian Elimination dags. Some example runs and automatically produced symbolic formulas for processor lower bounds by the algorithm are given.
{"title":"Automatic processor lower bound formulas for array computations","authors":"P. Cappello, Ö. Eğecioğlu","doi":"10.1109/ISPAN.2002.1004261","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004261","url":null,"abstract":"In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequence of dags and linear schedules parameterized by n, compute a lower bound on the number of processors required by the schedule as a function of n. This problem is formulated so that the number of tasks that are scheduled for execution during any fixed time step is the number of non-negative integer solutions d/sub n/ to a set of parametric linear Diophantine equations. Generating function methods are then used for constructing a formula for the numbers dn. We implemented this algorithm as a Mathematica program. This paper is an overview of the techniques involved and their applications to well-known schedules for Matrix-Vector Product, Triangular Matrix Product, and Gaussian Elimination dags. Some example runs and automatically produced symbolic formulas for processor lower bounds by the algorithm are given.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004306
N. Shaikh-Husin, M. Hani, Teoh Giap Seng
This paper describes the architecture and implementation of a shortest-path processor, both in reconfigurable hardware and VLSI. This processor is based on the principles of a recurrent spatiotemporal neural network. The processor's operation is similar to E.W. Dijkstra's (1959) algorithm and it can be used for network routing calculations. The objective of the processor is to find the least-cost path in a weighted graph between a given node and one or more destinations. The digital implementation, which exhibits a regular interconnect structure and uses simple processing elements, is well-suited for VLSI implementation and reconfigurable hardware.
{"title":"Implementation of recurrent neural network algorithm for shortest path calculation in network routing","authors":"N. Shaikh-Husin, M. Hani, Teoh Giap Seng","doi":"10.1109/ISPAN.2002.1004306","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004306","url":null,"abstract":"This paper describes the architecture and implementation of a shortest-path processor, both in reconfigurable hardware and VLSI. This processor is based on the principles of a recurrent spatiotemporal neural network. The processor's operation is similar to E.W. Dijkstra's (1959) algorithm and it can be used for network routing calculations. The objective of the processor is to find the least-cost path in a weighted graph between a given node and one or more destinations. The digital implementation, which exhibits a regular interconnect structure and uses simple processing elements, is well-suited for VLSI implementation and reconfigurable hardware.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122154689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004283
Wee-Chong Oon, A. Lim
Scheduling problems involve the allocation of limited resources to competing consumers. In real-life scheduling problems, these consumers often have their own dissimilar objective functions. As current techniques aim to maximize some weighted sum performance metric, these dissimilar objectives are not properly taken into account. Ideally, such problems should be solved by having all parties negotiate for the resources in a fair manner, with an impartial arbiter to oversee proceedings. This paper investigates an approach that simulates this "negotiation table" method of scheduling by modeling the problem into a multi-player collaborative cum competitive game.
{"title":"Multi-player game approach to scheduling problems","authors":"Wee-Chong Oon, A. Lim","doi":"10.1109/ISPAN.2002.1004283","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004283","url":null,"abstract":"Scheduling problems involve the allocation of limited resources to competing consumers. In real-life scheduling problems, these consumers often have their own dissimilar objective functions. As current techniques aim to maximize some weighted sum performance metric, these dissimilar objectives are not properly taken into account. Ideally, such problems should be solved by having all parties negotiate for the resources in a fair manner, with an impartial arbiter to oversee proceedings. This paper investigates an approach that simulates this \"negotiation table\" method of scheduling by modeling the problem into a multi-player collaborative cum competitive game.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122665059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004268
Jinhyuk Yoon, S. Min, Yookun Cho
Efficient and effective management of the buffer cache in the operating system becomes increasingly important as the speed gap between microprocessors and hard disks becomes wider This paper presents different techniques for predicting the future disk access patterns from the access history of each block and the access patterns detected for related blocks. The first part of the paper focuses on a block replacement policy called LRFU (least recently/frequently used) that subsumes the well-known LRU (least recently used) and the LFU (least frequently used) policies. Then, the next part discusses techniques for handling regular references such as sequential and looping references. Finally, the results from both trace-driven simulations and our implementation of the techniques within a real operating system are presented.
{"title":"Buffer cache management: predicting the future from the past","authors":"Jinhyuk Yoon, S. Min, Yookun Cho","doi":"10.1109/ISPAN.2002.1004268","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004268","url":null,"abstract":"Efficient and effective management of the buffer cache in the operating system becomes increasingly important as the speed gap between microprocessors and hard disks becomes wider This paper presents different techniques for predicting the future disk access patterns from the access history of each block and the access patterns detected for related blocks. The first part of the paper focuses on a block replacement policy called LRFU (least recently/frequently used) that subsumes the well-known LRU (least recently used) and the LFU (least frequently used) policies. Then, the next part discusses techniques for handling regular references such as sequential and looping references. Finally, the results from both trace-driven simulations and our implementation of the techniques within a real operating system are presented.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"1998 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117027714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004263
K. Nakano, S. Olariu
A radio network is a distributed system with no central arbiter, consisting of n radio transceivers, referred to as stations. We assume that the stations are identical and cannot be distinguished by serial or manufacturing number. The leader election problem asks to designate one of the stations as leader. In this work, we focus on single-channel, single-hop radio networks. We assume that time is slotted and all transmissions occur at slot boundaries. In each time slot the stations trans-init on the channel with some probability until, eventually, one of the stations is the declared leader. The history of a station up to time slot t is captured by the status of the channel and the transmission activity of the station in each of the t time slots. From the perspective of how much of the history information is used, we identify three types of leader election protocols for single-channel, single-hop radio networks: oblivious if no history information is used, uniform if only the history of the status of the channel is used, and nonuniform if the stations use both the status of channel and the transmission activity. The main goal of this paper is to provide a survey of recent leader election protocols for radio networks.
{"title":"A survey on leader election protocols for radio networks","authors":"K. Nakano, S. Olariu","doi":"10.1109/ISPAN.2002.1004263","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004263","url":null,"abstract":"A radio network is a distributed system with no central arbiter, consisting of n radio transceivers, referred to as stations. We assume that the stations are identical and cannot be distinguished by serial or manufacturing number. The leader election problem asks to designate one of the stations as leader. In this work, we focus on single-channel, single-hop radio networks. We assume that time is slotted and all transmissions occur at slot boundaries. In each time slot the stations trans-init on the channel with some probability until, eventually, one of the stations is the declared leader. The history of a station up to time slot t is captured by the status of the channel and the transmission activity of the station in each of the t time slots. From the perspective of how much of the history information is used, we identify three types of leader election protocols for single-channel, single-hop radio networks: oblivious if no history information is used, uniform if only the history of the status of the channel is used, and nonuniform if the stations use both the status of channel and the transmission activity. The main goal of this paper is to provide a survey of recent leader election protocols for radio networks.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130531509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISPAN.2002.1004279
Chun-Nan Hung, K. Liang, Lih-Hsing Hsu
The use of pancake and star networks as an interconnection network has been studied by many researchers. The fault tolerance for Hamiltonian networks is also an important issue. In this paper, we prove that an n-dimensional faulty pancake graph contains a Hamiltonian cycle with |F| /spl les/ n - 3 faults. Furthermore, there exist Hamiltonian paths between two arbitrary but distinct nodes in a faulty pancake graph with |F| /spl les/ n - 4 faults.
许多研究者已经研究了将煎饼和星形网络作为互连网络。哈密顿网络的容错性也是一个重要的问题。本文证明了一个n维故障煎饼图包含一个具有|F| /spl les/ n- 3个故障的哈密顿循环。此外，在一个含有F /spl / n - 4个故障的故障煎饼图中，两个任意但不同的节点之间存在哈密顿路径。
{"title":"Embedding Hamiltonian paths and Hamiltonian cycles in faulty pancake graphs","authors":"Chun-Nan Hung, K. Liang, Lih-Hsing Hsu","doi":"10.1109/ISPAN.2002.1004279","DOIUrl":"https://doi.org/10.1109/ISPAN.2002.1004279","url":null,"abstract":"The use of pancake and star networks as an interconnection network has been studied by many researchers. The fault tolerance for Hamiltonian networks is also an important issue. In this paper, we prove that an n-dimensional faulty pancake graph contains a Hamiltonian cycle with |F| /spl les/ n - 3 faults. Furthermore, there exist Hamiltonian paths between two arbitrary but distinct nodes in a faulty pancake graph with |F| /spl les/ n - 4 faults.","PeriodicalId":255069,"journal":{"name":"Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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