Pub Date : 2007-11-19DOI: 10.1109/ISPCS.2007.4383766
Kang B. Lee, E. Song
The IEEE 1588 standard specifies a protocol enabling precise synchronization of clocks in measurement and control systems implemented with technologies such as network communication, and distributed objects. The Unified Modeling Language (UML) is a powerful tool for object-oriented modeling, design, and development of complex distributed systems. This paper describes an object-oriented model for the IEEE 1588 standard-v2, which has been developed using UML tool at National Institute of Standards and Technology (NIST). Tliis model consists of the data types, datasets, entities, and devices of IEEE 1588 standard-v2. The model has been used to produce C++ source codes, and create C++ libraries for the IEEE 1588 standard-v2. With the help of this object model, the development time of IEEE 1588-basd distributed measurement and control applications can be reduced dramatically.
{"title":"Object-oriented Model for IEEE 1588 Standard","authors":"Kang B. Lee, E. Song","doi":"10.1109/ISPCS.2007.4383766","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383766","url":null,"abstract":"The IEEE 1588 standard specifies a protocol enabling precise synchronization of clocks in measurement and control systems implemented with technologies such as network communication, and distributed objects. The Unified Modeling Language (UML) is a powerful tool for object-oriented modeling, design, and development of complex distributed systems. This paper describes an object-oriented model for the IEEE 1588 standard-v2, which has been developed using UML tool at National Institute of Standards and Technology (NIST). Tliis model consists of the data types, datasets, entities, and devices of IEEE 1588 standard-v2. The model has been used to produce C++ source codes, and create C++ libraries for the IEEE 1588 standard-v2. With the help of this object model, the development time of IEEE 1588-basd distributed measurement and control applications can be reduced dramatically.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114485418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-19DOI: 10.1109/ISPCS.2007.4383776
T. Kurz, R. Hornstein, H. Schweinzer, M. Balik, M. Mayer
The ETCS standard was released by the European Union to reach interoperability in European railway signaling systems. This standard uses so called Eurobalises to send locally stored information to the passing train. Eurobalises are track mounted devices that operate on transponder technology. In order to support the standard for the European train control system (ETCS), a subsystem on the train called balise transmission module (BTM) was developed. The duty of the BTM is to tele-power an Eurobalise as the train passes and to receive the information sent by the Eurobalise. This data has to be demodulated and passed to the European vital computer (EVC), which is the control unit of the locomotive ensuring safe operation. To be able to locate a Eurobalise independent of received telegrams, a Balise Detect signal has to be additionally created by the BTM and sent to the EVC as demanded by ETCS standard. This signal is generated if the received field strength exceeds a given reference level. All components within the ETCS are operating in different time domains. In order to be able to calculate correct timing and odometric data, different time domains have to be synchronized. This has even effect on the safety critical operations within the system. ETCS requires the whole system fulfilling the SIL4 criteria. Considering modularity, it was decided that the BTM has to fulfill SIL4 criteria on its own, too. The crucial aspect is combining safety demands and time synchronization. It affects the communication between the BTM and the EVC. This paper focuses on the synchronization mechanisms within the components of the BTM and the synchronization between BTM and EVC.
{"title":"Time Synchronization in the Eurobalise Subsystem","authors":"T. Kurz, R. Hornstein, H. Schweinzer, M. Balik, M. Mayer","doi":"10.1109/ISPCS.2007.4383776","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383776","url":null,"abstract":"The ETCS standard was released by the European Union to reach interoperability in European railway signaling systems. This standard uses so called Eurobalises to send locally stored information to the passing train. Eurobalises are track mounted devices that operate on transponder technology. In order to support the standard for the European train control system (ETCS), a subsystem on the train called balise transmission module (BTM) was developed. The duty of the BTM is to tele-power an Eurobalise as the train passes and to receive the information sent by the Eurobalise. This data has to be demodulated and passed to the European vital computer (EVC), which is the control unit of the locomotive ensuring safe operation. To be able to locate a Eurobalise independent of received telegrams, a Balise Detect signal has to be additionally created by the BTM and sent to the EVC as demanded by ETCS standard. This signal is generated if the received field strength exceeds a given reference level. All components within the ETCS are operating in different time domains. In order to be able to calculate correct timing and odometric data, different time domains have to be synchronized. This has even effect on the safety critical operations within the system. ETCS requires the whole system fulfilling the SIL4 criteria. Considering modularity, it was decided that the BTM has to fulfill SIL4 criteria on its own, too. The crucial aspect is combining safety demands and time synchronization. It affects the communication between the BTM and the EVC. This paper focuses on the synchronization mechanisms within the components of the BTM and the synchronization between BTM and EVC.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-19DOI: 10.1109/ISPCS.2007.4383765
J. Eidson, J. Mackay, G. Garner, V. Skendzic
The protocol specified in IEEE 1588, together with a profile, define a timing system that may be used to supply precise timing to applications. However, IEEE 1588 does not say anything about the interface to the applications. In designing this interface, the application performance requirements (e.g., jitter, wander, time synchronization) must be considered. For example, an application that requires microsecond or better time synchronization needs a hardware or firmware interface; a software interface can result in exceeding the synchronization requirement by a factor of 1000 or more. This paper describes the performance requirements of example applications. It then describes a general application interface in abstract terms. Finally, it describes realizations of the interface that can meet the performance requirements for selected applications.
{"title":"Provision of Precise Timing via IEEE 1588 Application Interfaces","authors":"J. Eidson, J. Mackay, G. Garner, V. Skendzic","doi":"10.1109/ISPCS.2007.4383765","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383765","url":null,"abstract":"The protocol specified in IEEE 1588, together with a profile, define a timing system that may be used to supply precise timing to applications. However, IEEE 1588 does not say anything about the interface to the applications. In designing this interface, the application performance requirements (e.g., jitter, wander, time synchronization) must be considered. For example, an application that requires microsecond or better time synchronization needs a hardware or firmware interface; a software interface can result in exceeding the synchronization requirement by a factor of 1000 or more. This paper describes the performance requirements of example applications. It then describes a general application interface in abstract terms. Finally, it describes realizations of the interface that can meet the performance requirements for selected applications.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124780238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-19DOI: 10.1109/ISPCS.2007.4383771
A. Ademaj, H. Kopetz
The time-triggered Ethernet unifies real-time and non-real-time traffic into a single communication architecture. We have built a prototype implementation of an FPGA TT-Ethernet switch and an FPGA TT Ethernet communication controller supporting a network bandwidth of 100 Mbit/sec. Time-Triggered Ethernet introduces two message classes, i) the standard event-triggered Ethernet messages, denoted as ET messages, and ii) the time-triggered Ethernet messages, denoted as TT messages. All TT messages are transmitted periodically and are scheduled a priori in a way that there are no conflicts on the network. The network handles these messages according to the cut-through paradigm. Computer nodes containing TT Ethernet communication controllers establish and maintain global time base. However nodes containing standard Ethernet controllers can be connected to a TT Ethernet system and can send ET messages without affecting the temporal properties of the TT messages. The global time format of the TT Ethernet deploys the UTC time format which is compatible with the time format of the IEEE 1588 standard. In these work we present how we deploy the IEEE 1588 in order to synchronize the TT Ethernet controllers which require a tight synchronization among them. Additionally the IEEE 1588 clock synchronization based protocol will be implemented at standard Ethernet controllers such that they can be establish and maintain a global time base.
{"title":"Time-Triggered Ethernet and IEEE 1588 Clock Synchronization","authors":"A. Ademaj, H. Kopetz","doi":"10.1109/ISPCS.2007.4383771","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383771","url":null,"abstract":"The time-triggered Ethernet unifies real-time and non-real-time traffic into a single communication architecture. We have built a prototype implementation of an FPGA TT-Ethernet switch and an FPGA TT Ethernet communication controller supporting a network bandwidth of 100 Mbit/sec. Time-Triggered Ethernet introduces two message classes, i) the standard event-triggered Ethernet messages, denoted as ET messages, and ii) the time-triggered Ethernet messages, denoted as TT messages. All TT messages are transmitted periodically and are scheduled a priori in a way that there are no conflicts on the network. The network handles these messages according to the cut-through paradigm. Computer nodes containing TT Ethernet communication controllers establish and maintain global time base. However nodes containing standard Ethernet controllers can be connected to a TT Ethernet system and can send ET messages without affecting the temporal properties of the TT messages. The global time format of the TT Ethernet deploys the UTC time format which is compatible with the time format of the IEEE 1588 standard. In these work we present how we deploy the IEEE 1588 in order to synchronize the TT Ethernet controllers which require a tight synchronization among them. Additionally the IEEE 1588 clock synchronization based protocol will be implemented at standard Ethernet controllers such that they can be establish and maintain a global time base.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124990248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-19DOI: 10.1109/ISPCS.2007.4383791
G. Giorgi, C. Narduzzi
In the paper we present a behavioral simulation of PTP synchronization, based on the OMNeT++ simulator. Node, link and traffic source behavior are represented by statistical source and flow models. This approach, which differs from most approaches to PTP analysis, allows to focus on fundamental aspects of analysis and can be useful to assess the suitability of PTP synchronization in relation to network architecture and operating conditions, as well as for the optimization of clock servo design.
{"title":"Modeling and Simulation Analysis of PTP Clock Servo","authors":"G. Giorgi, C. Narduzzi","doi":"10.1109/ISPCS.2007.4383791","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383791","url":null,"abstract":"In the paper we present a behavioral simulation of PTP synchronization, based on the OMNeT++ simulator. Node, link and traffic source behavior are represented by statistical source and flow models. This approach, which differs from most approaches to PTP analysis, allows to focus on fundamental aspects of analysis and can be useful to assess the suitability of PTP synchronization in relation to network architecture and operating conditions, as well as for the optimization of clock servo design.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115612677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-19DOI: 10.1109/ISPCS.2007.4383778
L. Cosart
Aspects of IEEE 1588 Version 2, in particular the provisions for unicast and for faster sync rates, when combined with hardware timestamping and a precision timing reference such as GPS, provide a powerful tool for studying packet latency and packet delay variation, both in the laboratory and in live production networks. Many devices found in telecom networks such as routers, multilayer switches, and DSL access multiplexers, as well as complex networks, do not lend themselves to study using exclusively the multicast of the original IEEE 1588 definition. Further, investigation of the temporal characteristics of packet delay variation benefits from the increased sync rates available in IEEE 1588v2. This paper presents results and analysis of measurements taken in laboratory networks and production networks in various locations throughout the world. Networks of various types ranging from Local Area Networks (LANs) to Wide Area Networks (WANs) are studied.
IEEE 1588 Version 2的各个方面，特别是对单播和更快同步速率的规定，当与硬件时间戳和精确定时参考(如GPS)相结合时，为在实验室和现场生产网络中研究数据包延迟和数据包延迟变化提供了强大的工具。电信网络中的许多设备，如路由器、多层交换机和DSL接入多路复用器，以及复杂的网络，都不适合专门使用原始IEEE 1588定义的多播进行研究。此外，对分组延迟变化的时间特性的研究得益于IEEE 1588v2中可用的增加的同步速率。本文介绍了在世界各地的实验室网络和生产网络中进行的测量结果和分析。研究了从局域网(LANs)到广域网(wan)的各种类型的网络。
{"title":"Precision Packet Delay Measurements Using IEEE 1588v2","authors":"L. Cosart","doi":"10.1109/ISPCS.2007.4383778","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383778","url":null,"abstract":"Aspects of IEEE 1588 Version 2, in particular the provisions for unicast and for faster sync rates, when combined with hardware timestamping and a precision timing reference such as GPS, provide a powerful tool for studying packet latency and packet delay variation, both in the laboratory and in live production networks. Many devices found in telecom networks such as routers, multilayer switches, and DSL access multiplexers, as well as complex networks, do not lend themselves to study using exclusively the multicast of the original IEEE 1588 definition. Further, investigation of the temporal characteristics of packet delay variation benefits from the increased sync rates available in IEEE 1588v2. This paper presents results and analysis of measurements taken in laboratory networks and production networks in various locations throughout the world. Networks of various types ranging from Local Area Networks (LANs) to Wide Area Networks (WANs) are studied.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124385254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-19DOI: 10.1109/ISPCS.2007.4383775
P. Loschmidt, G. Gaderer, T. Sauter
The paper presents an innovative method to detect the position of commercial-off-the-shelf (COTS) wireless 802.1 la/b/g client hardware by evaluating differential signal propagation delays, thereby enhancing security or safety in wireless networks. The measurement is done by detecting the arrival time of a client signal at precisely synchronized access points. The overall vision is to accurately determine the position of a sender as a basis for new techniques for access control and system security as well as location based services in wireless environments. Safety-critical applications, like the task to make machines accepting commands only from operators located within the range of the machine, can be implemented. Furthermore, a security architecture can use such location information in order to offer services such as position based access policies, VLANs (Virtual Local Area Network), or Internet connections defining precise spatial coverage.
{"title":"Clock Synchronization for Wireless Positioning of COTS Mobile Nodes","authors":"P. Loschmidt, G. Gaderer, T. Sauter","doi":"10.1109/ISPCS.2007.4383775","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383775","url":null,"abstract":"The paper presents an innovative method to detect the position of commercial-off-the-shelf (COTS) wireless 802.1 la/b/g client hardware by evaluating differential signal propagation delays, thereby enhancing security or safety in wireless networks. The measurement is done by detecting the arrival time of a client signal at precisely synchronized access points. The overall vision is to accurately determine the position of a sender as a basis for new techniques for access control and system security as well as location based services in wireless environments. Safety-critical applications, like the task to make machines accepting commands only from operators located within the range of the machine, can be implemented. Furthermore, a security architecture can use such location information in order to offer services such as position based access policies, VLANs (Virtual Local Area Network), or Internet connections defining precise spatial coverage.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115123583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISPCS.2007.4383779
K. Schmidt
In the literature, one can find many recommendations for clock designs for either fully HW assisted IEEE 1588 systems or embedded SW implementations. The focus of such solutions is mostly on improving the synchronization performance. However, in most test and measurement systems, the main problem is not synchronization of clocks, but triggering of devices: even on a general purpose OS like Windows XPreg it is always possible to find a clock source with a sufficient resolution of around 1 mus for a SW-only IEEE 1588 implementation, but none of the built-in timers is suitable for triggering the device with such a resolution. In this paper, we will discuss the limits of timers under Windows XPreg and introduce an FPGA based timing HW as assistance for an IEEE 1588 SW implementation for use in Rohde&Schwarz FSL spectrum analyzers.
{"title":"IEEE 1588 on Windows XP® Powered Measurement Devices - Mastering the Trigger Challenge","authors":"K. Schmidt","doi":"10.1109/ISPCS.2007.4383779","DOIUrl":"https://doi.org/10.1109/ISPCS.2007.4383779","url":null,"abstract":"In the literature, one can find many recommendations for clock designs for either fully HW assisted IEEE 1588 systems or embedded SW implementations. The focus of such solutions is mostly on improving the synchronization performance. However, in most test and measurement systems, the main problem is not synchronization of clocks, but triggering of devices: even on a general purpose OS like Windows XPreg it is always possible to find a clock source with a sufficient resolution of around 1 mus for a SW-only IEEE 1588 implementation, but none of the built-in timers is suitable for triggering the device with such a resolution. In this paper, we will discuss the limits of timers under Windows XPreg and introduce an FPGA based timing HW as assistance for an IEEE 1588 SW implementation for use in Rohde&Schwarz FSL spectrum analyzers.","PeriodicalId":258197,"journal":{"name":"2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132473783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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