Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218568
Y. Wu
Based on information theoretic principles, metrics for 'super performance' signal processing systems design are developed. Conventional super computer systems figures-of-merit in throughput measures, MFLOPS or GFLOPS, do not consider these basic metrics. The issue in the design of a signal processing system is efficiency rather than raw processing speed. The critical parameters to consider in designing a signal processing system are the available power and communications resources.<>
{"title":"On metrics of 'super performance' (signal processing systems)","authors":"Y. Wu","doi":"10.1109/ASAP.1992.218568","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218568","url":null,"abstract":"Based on information theoretic principles, metrics for 'super performance' signal processing systems design are developed. Conventional super computer systems figures-of-merit in throughput measures, MFLOPS or GFLOPS, do not consider these basic metrics. The issue in the design of a signal processing system is efficiency rather than raw processing speed. The critical parameters to consider in designing a signal processing system are the available power and communications resources.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122373561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218554
F. Lorenzelli, K. Yao, T. Chan, P. Hansen
In many fields of signal and image processing control, and telecommunication there is much interest today in the numerical techniques offered by linear algebra. The singular value decomposition (SVD) is one of the techniques which have proven useful in many engineering applications, but unfortunately its computation is a costly procedure. The QR factorization (QRF) requires much less computational effort, but rank and null-space estimates are not necessarily reliable. This paper presents a version of rank revealing QR (RRQR) algorithm which is suited for implementation on a VLSI systolic array. The implementation of the RRQRF requires n(n+1)/2 processors and O(n) external buffers, for a problem of order n. The execution time for the algorithm is O(nr), where r is A's numerical rank.<>
{"title":"A systolic rank revealing QR algorithm","authors":"F. Lorenzelli, K. Yao, T. Chan, P. Hansen","doi":"10.1109/ASAP.1992.218554","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218554","url":null,"abstract":"In many fields of signal and image processing control, and telecommunication there is much interest today in the numerical techniques offered by linear algebra. The singular value decomposition (SVD) is one of the techniques which have proven useful in many engineering applications, but unfortunately its computation is a costly procedure. The QR factorization (QRF) requires much less computational effort, but rank and null-space estimates are not necessarily reliable. This paper presents a version of rank revealing QR (RRQR) algorithm which is suited for implementation on a VLSI systolic array. The implementation of the RRQRF requires n(n+1)/2 processors and O(n) external buffers, for a problem of order n. The execution time for the algorithm is O(nr), where r is A's numerical rank.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218543
W. Luk
This paper describes a design framework for developing application-specific serial array circuits. Starting from a description of the state-transition logic or a fully-parallel architecture, correctness-preserving transformations are employed to derive a wide range of implementations with different space-time trade-offs. The approach has been used in synthesising designs based on field-programmable gate arrays, and is illustrated by the development of a number of circuits including sorters and convolvers.<>
{"title":"Transformation techniques for serial array design","authors":"W. Luk","doi":"10.1109/ASAP.1992.218543","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218543","url":null,"abstract":"This paper describes a design framework for developing application-specific serial array circuits. Starting from a description of the state-transition logic or a fully-parallel architecture, correctness-preserving transformations are employed to derive a wide range of implementations with different space-time trade-offs. The approach has been used in synthesising designs based on field-programmable gate arrays, and is illustrated by the development of a number of circuits including sorters and convolvers.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116303035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218551
P. Fitzpatrick, Colin C. Murphy
The authors present a fault tolerant algorithm for the solution of linear systems of equations using matrix triangularization procedures suitable for implementation on array architectures. Gaussian elimination with partial or pairwise pivoting and QR decomposition are made fault tolerant against two transient errors occurring during the triangularization procedure. The extended Euclidean algorithm is implemented to solve for the locations and values of the errors defined appropriately using the theory of error correcting codes. The Sherman-Morrison Woodbury formula is then used to obtain the correct solution vector to the linear system of equations without requiring a valid decomposition.<>
{"title":"Fault tolerant matrix triangularization and solution of linear systems of equations","authors":"P. Fitzpatrick, Colin C. Murphy","doi":"10.1109/ASAP.1992.218551","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218551","url":null,"abstract":"The authors present a fault tolerant algorithm for the solution of linear systems of equations using matrix triangularization procedures suitable for implementation on array architectures. Gaussian elimination with partial or pairwise pivoting and QR decomposition are made fault tolerant against two transient errors occurring during the triangularization procedure. The extended Euclidean algorithm is implemented to solve for the locations and values of the errors defined appropriately using the theory of error correcting codes. The Sherman-Morrison Woodbury formula is then used to obtain the correct solution vector to the linear system of equations without requiring a valid decomposition.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130464016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-08-04DOI: 10.1109/ASAP.1992.218542
H. Printz
The author discusses the design of a program that maps a class of digital signal processing systems, called narrowband spectral detection systems, to linear MIMD machines. Such systems contain a mixture of data-parallel, systolic and purely serial computations. He describes a new technique, called geometric scheduling, that exploits the special features of the first two styles of computation, and that can also incorporate tasks that are neither data-parallel nor systolic. The resulting schedules contain all necessary communication code, which is automatically generated. This paper includes performance figures for this method on a typical narrowband spectral detection system.<>
{"title":"Compilation of narrowband spectral detection systems for linear MIMD machines","authors":"H. Printz","doi":"10.1109/ASAP.1992.218542","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218542","url":null,"abstract":"The author discusses the design of a program that maps a class of digital signal processing systems, called narrowband spectral detection systems, to linear MIMD machines. Such systems contain a mixture of data-parallel, systolic and purely serial computations. He describes a new technique, called geometric scheduling, that exploits the special features of the first two styles of computation, and that can also incorporate tasks that are neither data-parallel nor systolic. The resulting schedules contain all necessary communication code, which is automatically generated. This paper includes performance figures for this method on a typical narrowband spectral detection system.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132149790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-18DOI: 10.1109/ASAP.1992.218565
C. Rader
This paper describes a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which the author calls MUSE, and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 dB of S/N improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI. The complete design of such a wafer is described.<>
{"title":"MUSE-a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer scale integration","authors":"C. Rader","doi":"10.1109/ASAP.1992.218565","DOIUrl":"https://doi.org/10.1109/ASAP.1992.218565","url":null,"abstract":"This paper describes a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which the author calls MUSE, and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 dB of S/N improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI. The complete design of such a wafer is described.<<ETX>>","PeriodicalId":265438,"journal":{"name":"[1992] Proceedings of the International Conference on Application Specific Array Processors","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131636556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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