This paper discusses a case study, the co-design of an ATM Network Interface Card (NIC). The NIC is aimed to interface applications with the physical network line. It is composed of a stack of four protocol layers: TCP, IP, AAL and ATM. In this study, the initial specification is given in a language called SDL. The architecture exploration is made using Cosmos, a co-design tool for multiprocessor architecture. Several architectures are produced starting from the same initial SDL specification. The performance evaluation of these solutions,vas made using C/VHDL co-simulation. This paper describes the experiment and the lessons learned about the capabilities and the restrictions of Cosmos and SDL. The use of SDL allows for drastic reduction of the model size when compared to C/VHDL model. SDL simulation may be 100 times faster than C/VHDL simulation. SDL provides powerful capabilities for system-level specification, but lacks facilities for the expression of DSP oriented computation.
{"title":"Hardware/software co-design of an ATM network interface card: a case study","authors":"J. Daveau, G. Marchioro, A. Jerraya","doi":"10.1109/HSC.1998.666247","DOIUrl":"https://doi.org/10.1109/HSC.1998.666247","url":null,"abstract":"This paper discusses a case study, the co-design of an ATM Network Interface Card (NIC). The NIC is aimed to interface applications with the physical network line. It is composed of a stack of four protocol layers: TCP, IP, AAL and ATM. In this study, the initial specification is given in a language called SDL. The architecture exploration is made using Cosmos, a co-design tool for multiprocessor architecture. Several architectures are produced starting from the same initial SDL specification. The performance evaluation of these solutions,vas made using C/VHDL co-simulation. This paper describes the experiment and the lessons learned about the capabilities and the restrictions of Cosmos and SDL. The use of SDL allows for drastic reduction of the model size when compared to C/VHDL model. SDL simulation may be 100 times faster than C/VHDL simulation. SDL provides powerful capabilities for system-level specification, but lacks facilities for the expression of DSP oriented computation.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123815499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present thread-based optimistic distributed timed cosimulation methods which reduce the overhead of optimistic simulation. First, we present a thread simulation model to facilitate efficient distributed cosimulation. To reduce the overhead of optimistic simulation, we focus on the reduction of state saving overhead. Based on the thread simulation model, we perform thread-level state saving without saving the whole state of processor at each check-point. Especially, single checkpoint property based on the proposed thread model minimizes the number of state savings for HW threads. We give preliminary experimental results to show the efficiency of the proposed methods.
{"title":"Optimistic distributed timed cosimulation based on thread simulation model","authors":"S. Yoo, Kiyoung Choi","doi":"10.1109/HSC.1998.666240","DOIUrl":"https://doi.org/10.1109/HSC.1998.666240","url":null,"abstract":"In this paper, we present thread-based optimistic distributed timed cosimulation methods which reduce the overhead of optimistic simulation. First, we present a thread simulation model to facilitate efficient distributed cosimulation. To reduce the overhead of optimistic simulation, we focus on the reduction of state saving overhead. Based on the thread simulation model, we perform thread-level state saving without saving the whole state of processor at each check-point. Especially, single checkpoint property based on the proposed thread model minimizes the number of state savings for HW threads. We give preliminary experimental results to show the efficiency of the proposed methods.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"464 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116509808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Passerone, R. Passerone, C. Sansoè, J. Martin, A. Sangiovanni-Vincentelli, Rick McGeer
We present an application of the Java/sup TM/ programming language to specify and implement reactive real-time systems. We have developed and tested a collection of classes and methods to describe concurrent modules and their asynchronous communication by means of signals. The control structures are closely patterned after those of the synchronous language Esterel, succinctly describing concurrency, sequencing and preemption. We show the user-friendliness and efficiency of the proposed technique by using an example from the automotive domain.
{"title":"Modeling reactive systems in Java","authors":"C. Passerone, R. Passerone, C. Sansoè, J. Martin, A. Sangiovanni-Vincentelli, Rick McGeer","doi":"10.1109/HSC.1998.666232","DOIUrl":"https://doi.org/10.1109/HSC.1998.666232","url":null,"abstract":"We present an application of the Java/sup TM/ programming language to specify and implement reactive real-time systems. We have developed and tested a collection of classes and methods to describe concurrent modules and their asynchronous communication by means of signals. The control structures are closely patterned after those of the synchronous language Esterel, succinctly describing concurrency, sequencing and preemption. We show the user-friendliness and efficiency of the proposed technique by using an example from the automotive domain.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125818295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocesser system based on off-the-shelf components as target architecture for an executable prototype, which is generated from the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.
{"title":"Towards interprocess communication and interface synthesis for a heterogeneous real-time rapid prototyping environment","authors":"F. Fischer, Annette Muth, G. Färber","doi":"10.1109/HSC.1998.666235","DOIUrl":"https://doi.org/10.1109/HSC.1998.666235","url":null,"abstract":"Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocesser system based on off-the-shelf components as target architecture for an executable prototype, which is generated from the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127045734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are automatically inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). An object-oriented approach is presented that enables an easy migration (retargeting) of typical communication primitives to other target architectures.
{"title":"Domain-specific interface generation from dataflow specifications","authors":"Michael Eisenring, J. Teich","doi":"10.1109/HSC.1998.666236","DOIUrl":"https://doi.org/10.1109/HSC.1998.666236","url":null,"abstract":"In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are automatically inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). An object-oriented approach is presented that enables an easy migration (retargeting) of typical communication primitives to other target architectures.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126008546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. Generally the aim is to provide solutions that respect timing constraints and minimize an objective function such as the total area and/or the power consumption. Minimizing the hardware area conflicts with reducing execution time. Therefore, we introduce an heuristic for synthesizing heterogeneous systems that uses a global metric to guide the mapping of tasks according to the reusability of components and the time margin induced by timing constraints.
{"title":"A path analysis based partitioning for time constrained embedded systems","authors":"L. Bianco, M. Auguin, G. Gogniat, A. Pegatoquet","doi":"10.1109/HSC.1998.666242","DOIUrl":"https://doi.org/10.1109/HSC.1998.666242","url":null,"abstract":"The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. Generally the aim is to provide solutions that respect timing constraints and minimize an objective function such as the total area and/or the power consumption. Minimizing the hardware area conflicts with reducing execution time. Therefore, we introduce an heuristic for synthesizing heterogeneous systems that uses a global metric to guide the mapping of tasks according to the reusability of components and the time margin induced by timing constraints.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130667102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill model allows for additional (money) cost, software code size and hardware area tradeoffs to be examined.
{"title":"Communication estimation for hardware/software codesign","authors":"P. Knudsen, J. Madsen","doi":"10.1109/HSC.1998.666238","DOIUrl":"https://doi.org/10.1109/HSC.1998.666238","url":null,"abstract":"This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill model allows for additional (money) cost, software code size and hardware area tradeoffs to be examined.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128615856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hardware accelerators) in one system. Interfacing hardware and software components together and providing communications between them are particularly error prone and time consuming tasks. Hence, on the basis of a generic architecture we propose an extended communication synthesis method that provides characterization of communications and their implementation scheme in the target architecture. This method takes place after partitioning and scheduling and can constitute the basis of a back end of a codesign framework leading to HW/SW integration.
{"title":"Communication synthesis and HW/SW integration for embedded system design","authors":"G. Gogniat, M. Auguin, L. Bianco, A. Pegatoquet","doi":"10.1109/HSC.1998.666237","DOIUrl":"https://doi.org/10.1109/HSC.1998.666237","url":null,"abstract":"The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hardware accelerators) in one system. Interfacing hardware and software components together and providing communications between them are particularly error prone and time consuming tasks. Hence, on the basis of a generic architecture we propose an extended communication synthesis method that provides characterization of communications and their implementation scheme in the target architecture. This method takes place after partitioning and scheduling and can constitute the basis of a back end of a codesign framework leading to HW/SW integration.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122494877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Energy dissipation is a hot topic in the design of- especially mobile-embedded systems. This is because applications like digital video cameras, cellular phones etc. draw their current from batteries that spend a limited amount of energy only. In this paper we show that energy-conscious HW/SW-partitioning can lead to drastic reductions of energy dissipation of a whole embedded system. Subject of investigation is an MPEG-2 encoder. Therefore, we introduce our framework for estimating and optimizing system energy as well as all conducted design steps. The obtained results show energy savings up 59% while the performance remains approximately the same or becomes even slightly higher. As a main result, energy-conscious HW/SW-partitioning is a promising method to be deployed in addition to classical energy and/or power reduction methods.
{"title":"Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder","authors":"J. Henkel, Yanbing Li","doi":"10.1109/HSC.1998.666233","DOIUrl":"https://doi.org/10.1109/HSC.1998.666233","url":null,"abstract":"Energy dissipation is a hot topic in the design of- especially mobile-embedded systems. This is because applications like digital video cameras, cellular phones etc. draw their current from batteries that spend a limited amount of energy only. In this paper we show that energy-conscious HW/SW-partitioning can lead to drastic reductions of energy dissipation of a whole embedded system. Subject of investigation is an MPEG-2 encoder. Therefore, we introduce our framework for estimating and optimizing system energy as well as all conducted design steps. The obtained results show energy savings up 59% while the performance remains approximately the same or becomes even slightly higher. As a main result, energy-conscious HW/SW-partitioning is a promising method to be deployed in addition to classical energy and/or power reduction methods.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123079178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Behavioral HDL descriptions from designers are structured in a program calling hierarchy for the purposes of programming convenience and conceptualization. This code structure is often not suitable for direct synthesis into digital hardware. For instance, information regarding operation exclusivity and resource sharing can be explored by restructuring the code. In this paper, we present a method to restructure behavioral HDL code using merging and decomposition of Timed Decision Tables (TDTs).
{"title":"HDL code restructuring using timed decision tables","authors":"Jian Li, Rajesh K. Gupta","doi":"10.1109/HSC.1998.666250","DOIUrl":"https://doi.org/10.1109/HSC.1998.666250","url":null,"abstract":"Behavioral HDL descriptions from designers are structured in a program calling hierarchy for the purposes of programming convenience and conceptualization. This code structure is often not suitable for direct synthesis into digital hardware. For instance, information regarding operation exclusivity and resource sharing can be explored by restructuring the code. In this paper, we present a method to restructure behavioral HDL code using merging and decomposition of Timed Decision Tables (TDTs).","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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