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Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)最新文献

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Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models 基于抽象状态机模型的复杂软硬件系统快速动态分析
G. D. Castillo, W. Hardt
High level design decisions as HW/SW-partitioning and instrumenting of building blocks can be supported efficiently by detailed analysis of dynamic instruction usage. In many cases the instruction usage is specific to the application domain in view. We present a very fast analysis approach based on high level system models. Complex application characteristics, e.g., the average number of not interrupted instructions can be determined. This is much more than execution of, for example, C-programs can provide.
通过对动态指令使用情况的详细分析,可以有效地支持构建块的硬件/软件分区和插装等高级设计决策。在许多情况下,指令的使用是特定于所查看的应用程序域的。我们提出了一种基于高层系统模型的快速分析方法。可以确定复杂的应用特性,例如,未中断指令的平均数量。这比执行,例如c程序所能提供的要多得多。
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引用次数: 6
Software timing analysis using HW/SW cosimulation and instruction set simulator 软件时序分析采用软硬件协同仿真和指令集模拟器
Jie Liu, M. Lajolo, A. Sangiovanni-Vincentelli
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculated by a software performance estimation method, which is not accurate enough for hard real-time systems and complicated designs. In this paper we present an approach to integrate a clock-cycle-accurate instruction set simulator (ISS) with a fast event-based system simulator. By using the ISS, the delay of events can be measured instead of estimated. An interprocess communication architecture and a simple protocol are designed to meet the requirement of robustness and flexibility. A cached refinement scheme is presented to improve the performance at the expense of accuracy. The scheme is especially effective for applications in which the delay of basic blocks is approximately data-independent. We also discuss the implementation issues by using the Ptolemy simulation environment and the ST20 simulator as an example.
在实时系统设计中,检验约束是否满足的时序分析是一个关键问题。在现有的一些方法中,软件模块的延迟是通过软件性能估计的方法来预计算的,对于硬实时系统和复杂的设计来说,这种方法不够精确。本文提出了一种将时钟周期精确指令集模拟器(ISS)与基于事件的快速系统模拟器相结合的方法。通过使用ISS,可以测量而不是估计事件的延迟。为了满足鲁棒性和灵活性的要求,设计了进程间通信体系结构和简单的协议。提出了一种以牺牲精度为代价来提高性能的缓存优化方案。该方案特别适用于基本块的延迟近似与数据无关的应用。本文还以托勒密仿真环境和ST20模拟器为例,讨论了实现问题。
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引用次数: 66
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns RECOD:在硬件/软件协同设计中优化资源和内存利用的重定时启发式算法
Karam S. Chatha, R. Vemuri
Hardware/software designs of embedded systems are characterized by stringent performance constraints. Pipelined implementation of a design is an effective way for maximizing the performance of a design. In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-software codesigns. The heuristic aims at maximizing the throughput of a loop oriented resource constrained codesign while minimizing its shared memory usage. The effectiveness of the proposed technique is demonstrated by experimentation.
嵌入式系统的硬件/软件设计具有严格的性能限制。设计的流水线实现是实现设计性能最大化的有效途径。本文提出了一种新的重定时启发式算法,用于硬件软件协同设计的流水线调度。启发式算法的目标是最大化面向循环的资源约束协同设计的吞吐量,同时最小化其共享内存的使用。实验证明了该方法的有效性。
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引用次数: 13
Schedulability analysis of heterogeneous systems for performance message sequence chart 异构系统性能消息序列图的可调度性分析
F. Slomka, J. Zant, L. Lambert
Telecommunication systems are often specified in the standardized languages SDL and MSC. These languages allow only the specification of pure functional aspects. To remedy this problem we have combined the language MSC and performance aspects in Performance MSC (PMSC). From a PMSC specification a task model can be derived that includes beside computation times, periods and deadlines of tasks, also absolute start times of tasks and dependencies between task. This allows us to apply an extended schedulability analysis of asynchronous tasks on heterogeneous target architectures. We present the analysis technique and demonstrate with a small example, how the algorithm can be used for the real-time analysis of a cordless telephone.
电信系统通常用标准化语言SDL和MSC来指定。这些语言只允许对纯函数方面进行规范。为了解决这个问题,我们在性能管理硕士(PMSC)中结合了语言管理硕士和性能方面。从PMSC规范中可以导出一个任务模型,该模型除了包括任务的计算时间、周期和截止日期外,还包括任务的绝对开始时间和任务之间的依赖关系。这允许我们对异构目标体系结构上的异步任务应用扩展的可调度性分析。我们提出了分析技术,并通过一个小例子证明了该算法如何用于无绳电话的实时分析。
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引用次数: 15
A hardware/software prototyping environment for dynamically reconfigurable embedded systems 用于动态可重构嵌入式系统的硬件/软件原型环境
Josef Fleischmann, K. Buchenrieder, Rainer Kress
Next generation embedded systems place new demands on an efficient methodology for their design and verification. These systems have to support interaction over a network, multiple concurrent applications and changing operating conditions. Therefore, besides existing requirements like low cost and high performance, new demands like adaptivity and reconfigurability arise. Traditional design methodologies do nor support exploration and implementation of this flavor of networked embedded systems. In this paper we present a suitable methodology and a flexible experimental environment which supports design exploration and prototyping of dynamically dynamically reconfigurable embedded systems based on Java specifications.
下一代嵌入式系统对其设计和验证的有效方法提出了新的要求。这些系统必须支持网络上的交互、多个并发应用程序和不断变化的操作条件。因此,除了现有的低成本、高性能等需求外,新的适应性、可重构性等需求也随之产生。传统的设计方法不支持探索和实现这种类型的网络化嵌入式系统。本文提出了一种合适的方法和灵活的实验环境,支持基于Java规范的动态可重构嵌入式系统的设计探索和原型设计。
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引用次数: 1
Combining multiple models of computation for scheduling and allocation 结合多种计算模型进行调度和分配
D. Ziegenbein, R. Ernst, K. Richter, J. Teich, L. Thiele
Many applications include a variety of functions from different domains. Therefore, they are best modeled with a combination of different modeling languages. For a sound design process and improved design space utilization, these different input models should be mapped to a common representation. In this paper, we present a common internal representation that integrates the aspects of several models of computation and is targeted to scheduling and allocation. The representation is explained using an example combining a classical process model as used in real-time operating systems (RTOS) with the synchronous data flow model (SDF).
许多应用程序包括来自不同领域的各种功能。因此,最好使用不同建模语言的组合对它们进行建模。为了健全的设计过程和改进的设计空间利用率,这些不同的输入模型应该映射到一个共同的表示。在本文中,我们提出了一个通用的内部表示,它集成了几个计算模型的各个方面,并针对调度和分配。通过将实时操作系统(RTOS)中使用的经典进程模型与同步数据流模型(SDF)相结合的示例来解释这种表示。
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引用次数: 44
A case study on modeling shared memory access effects during performance analysis of HW/SW systems 硬件/软件系统性能分析中共享内存访问效果建模的案例研究
M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, A. Sangiovanni-Vincentelli
Behavioral simulation with timing annotations derived from performance modeling and analysis is a promising alternative for use in evaluating system-level design trade-offs. The accuracy of such approaches is determined by how well the effects of various HW and SW architectural features, like the Real Time Operating System (RTOS), shared memories and buses, HW/SW communication mechanisms, etc are modeled at this level. We present a study of the effects of shared memory buses during system-level performance analysis in the POLIS co-design environment using the example of a TCP/IP Network Interface System. We demonstrate how the effects of the memory arbiter and shared memory bus can be modeled efficiently at the behavioral level, and used to evaluate various design tradeoffs. Experimental results demonstrate that modeling these effects can significantly increase the accuracy of system-level performance estimates.
带有从性能建模和分析派生的定时注释的行为模拟是用于评估系统级设计权衡的一种很有前途的替代方法。这种方法的准确性取决于各种硬件和软件架构特性的效果,如实时操作系统(RTOS)、共享内存和总线、硬件/软件通信机制等在这个级别上建模的效果。我们以TCP/IP网络接口系统为例,对POLIS协同设计环境中系统级性能分析期间共享内存总线的影响进行了研究。我们演示了如何在行为级别有效地对内存仲裁器和共享内存总线的影响进行建模,并用于评估各种设计权衡。实验结果表明,对这些效应进行建模可以显著提高系统级性能估计的准确性。
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引用次数: 27
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems HiPART:用于实时嵌入式系统的一种新的分层半交互式硬件/软件划分方法,具有快速调试功能
T. Hollstein, J. Becker, A. Kirschbaum, M. Glesner
In this contribution we present a new system-level hardware/software partitioning approach (HiPART) which is run in the frame of an integrated hardware software design methodology for embedded system design. The benefits of the approach result from an hierarchical partitioning algorithm, consisting of three phases of constructive and iterative methods. The main advantage of the system is a freely selectable degree of user interaction and manual partitioning. A permanent observation of timing constraint violations during partitioning guarantees the applicability for real-time systems.
在本文中,我们提出了一种新的系统级硬件/软件分区方法(HiPART),该方法在嵌入式系统设计的集成硬件软件设计方法框架中运行。该方法的优点来自于分层划分算法,包括三个阶段的构造和迭代方法。该系统的主要优点是可以自由选择用户交互和手动分区的程度。在分区期间对时间约束违反的永久观察保证了对实时系统的适用性。
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引用次数: 21
An analysis-based approach to composition of distributed embedded systems 基于分析的分布式嵌入式系统组成方法
P. Chou, G. Borriello
The growing complexity in the functionality and system architecture of embedded systems has motivated designers to raise the level of abstraction by composing the system with a mix of reusable and system-specific components. Currently, these components assume specific programming models that make them difficult to compose or retarget. The modal process model addresses the problem of control composition by separating the synchronization semantics from state unification, and by supporting automatic synthesis of control communication onto distributed architectures. By avoiding over-specifying the behavior, the components can be made more composable and the designer can more easily choose the least expensive synchronization semantics for implementing the composition. To help designers evaluate their choice, we propose a method for analyzing the properties of the composed system, including the detection of potential deadlock and livelock situations.
嵌入式系统的功能和系统架构日益复杂,这促使设计人员通过使用可重用和系统特定组件的混合组合系统来提高抽象级别。目前,这些组件采用特定的编程模型,这使得它们难以组合或重新定位。模态过程模型通过将同步语义与状态统一分离,并支持在分布式体系结构上自动合成控制通信,解决了控制组合的问题。通过避免过度指定行为,可以使组件更具可组合性,并且设计人员可以更容易地选择成本最低的同步语义来实现组合。为了帮助设计人员评估他们的选择,我们提出了一种分析组合系统属性的方法,包括检测潜在的死锁和活锁情况。
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引用次数: 11
TGFF: task graphs for free TGFF:免费的任务图
R. Dick, D. Rhodes, W. Wolf
We present a user-controllable, general-purpose, pseudorandom task graph generator called Task Graphs For Free (TGFF). TGFF creates problem instances for use in allocation and scheduling research. It has the ability to generate independent tasks as well as task sets which are composed of partially ordered task graphs. A complete description of a scheduling problem instance is created, including attributes for processors, communication resources, tasks, and inter-task communication. The user may parametrically control the correlations between attributes. Sharing TGFF's parameter settings allows researchers to easily reproduce the examples used by others, regardless of the platform on which TGFF is run.
我们提出了一个用户可控的、通用的、伪随机的任务图生成器,称为任务图免费(TGFF)。TGFF创建用于分配和调度研究的问题实例。它具有生成独立任务以及由部分有序任务图组成的任务集的能力。创建调度问题实例的完整描述,包括处理器、通信资源、任务和任务间通信的属性。用户可以参数化地控制属性之间的相关性。共享TGFF的参数设置使研究人员可以轻松地复制其他人使用的示例,而不管TGFF运行在哪个平台上。
{"title":"TGFF: task graphs for free","authors":"R. Dick, D. Rhodes, W. Wolf","doi":"10.1109/HSC.1998.666245","DOIUrl":"https://doi.org/10.1109/HSC.1998.666245","url":null,"abstract":"We present a user-controllable, general-purpose, pseudorandom task graph generator called Task Graphs For Free (TGFF). TGFF creates problem instances for use in allocation and scheduling research. It has the ability to generate independent tasks as well as task sets which are composed of partially ordered task graphs. A complete description of a scheduling problem instance is created, including attributes for processors, communication resources, tasks, and inter-task communication. The user may parametrically control the correlations between attributes. Sharing TGFF's parameter settings allows researchers to easily reproduce the examples used by others, regardless of the platform on which TGFF is run.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125792277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 998
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Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)
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