The wide usage of hardware intellectual property (IP) cores from untrusted vendors has raised security concerns in the integrated circuit (IC) industry. Existing testing methods are designed to validate the functionality of the hardware IP cores. These methods often fall short in detecting unspecified (often malicious) logic. Formal methods, on the other hand, can help eliminate hardware Trojans and/or design backdoors by formally proving security properties on soft IP cores despite the high proof development cost. To alleviate the computation burden, we propose a new hierarchy-preserving formal verification (HiFV) framework for circuit trust evaluation at the pre-silicon stage. This framework is derived from the Proof-Carrying Hardware (PCH) and is dedicated for security property verification of System-on-Chip (SoC) platforms, where third-party soft IPs are integrated as sub-modules. The key novelty lies in the improvement of the proof construction process of the previously developed security property verification framework, so that the framework can support building theorem proofs in a hierarchical way. We assume a trusted third-party verification house exists, which can use the proposed framework for security theorem construction and proof writing. The applicability of the proposed framework is demonstrated by formally verifying the memory integrity property on an 8051 microprocessor whose sub-modules were treated as untrusted third-party IPs.
{"title":"Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance","authors":"Xiaolong Guo, R. Dutta, Yier Jin","doi":"10.1109/MTV.2015.12","DOIUrl":"https://doi.org/10.1109/MTV.2015.12","url":null,"abstract":"The wide usage of hardware intellectual property (IP) cores from untrusted vendors has raised security concerns in the integrated circuit (IC) industry. Existing testing methods are designed to validate the functionality of the hardware IP cores. These methods often fall short in detecting unspecified (often malicious) logic. Formal methods, on the other hand, can help eliminate hardware Trojans and/or design backdoors by formally proving security properties on soft IP cores despite the high proof development cost. To alleviate the computation burden, we propose a new hierarchy-preserving formal verification (HiFV) framework for circuit trust evaluation at the pre-silicon stage. This framework is derived from the Proof-Carrying Hardware (PCH) and is dedicated for security property verification of System-on-Chip (SoC) platforms, where third-party soft IPs are integrated as sub-modules. The key novelty lies in the improvement of the proof construction process of the previously developed security property verification framework, so that the framework can support building theorem proofs in a hierarchical way. We assume a trusted third-party verification house exists, which can use the proposed framework for security theorem construction and proof writing. The applicability of the proposed framework is demonstrated by formally verifying the memory integrity property on an 8051 microprocessor whose sub-modules were treated as untrusted third-party IPs.","PeriodicalId":273432,"journal":{"name":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130408209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the co-simulation methodology adopted for hardware verification of a next generation network packet processing engine (Advanced I/O Processor or AIOP) utilizing virtual prototype models developed originally for software verification. Though co-simulation strategies are common in verification of stand-alone processors, they have seldom been used for mega-modules and SoC, which consist of large number of cores and accelerators like the AIOP. The cosimulation platform containing the AIOP functional model is used as a dynamic scoreboard in the top-level Universal Verification Methodology (UVM) test-bench. Since functional models are untimed or loosely-timed, the primary challenge here is to maintain synchronization between the design-under-test (DUT) and the functional model. This paper describes in detail the synchronization challenges encountered while running multicore software and how they were solved with minimal sacrifice to verification quality. Using this methodology, we unearthed more than 15 critical bugs in the DUT as well as large number of issues in the software libraries and functional models.
{"title":"Leveraging Virtual Prototype Models for Hardware Verification of an Accelerated Network Packet Processing Engine","authors":"Sourav Roy, Nikhil Jain, Sandeep Jain, RobertE Page","doi":"10.1109/MTV.2015.17","DOIUrl":"https://doi.org/10.1109/MTV.2015.17","url":null,"abstract":"This paper describes the co-simulation methodology adopted for hardware verification of a next generation network packet processing engine (Advanced I/O Processor or AIOP) utilizing virtual prototype models developed originally for software verification. Though co-simulation strategies are common in verification of stand-alone processors, they have seldom been used for mega-modules and SoC, which consist of large number of cores and accelerators like the AIOP. The cosimulation platform containing the AIOP functional model is used as a dynamic scoreboard in the top-level Universal Verification Methodology (UVM) test-bench. Since functional models are untimed or loosely-timed, the primary challenge here is to maintain synchronization between the design-under-test (DUT) and the functional model. This paper describes in detail the synchronization challenges encountered while running multicore software and how they were solved with minimal sacrifice to verification quality. Using this methodology, we unearthed more than 15 critical bugs in the DUT as well as large number of issues in the software libraries and functional models.","PeriodicalId":273432,"journal":{"name":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132314474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Our team has been developing a System on a Chip (SoC) and is using Synopsys VDK to accelerate both software development and hardware verification. We will discuss how VDK has helped us achieve our primary goal of starting software development and testing prior to design fabrication and our secondary goal of testing our RTL with software. The platform creation process and our transition from RTL-only to Transaction-Level-with-RTL co-simulations will be briefly discussed to provide background. We will also compare our efforts prototyping our design on FPGAs to our experience using VDK. The integration of VDK with an RTL simulator has provided a good balance of simulation speed and visibility down into the design and our engineers have been able to run design validation testing (DVT) software on a large portion of our final RTL prior to our tape out.
{"title":"SoC Development and Prototype with VDK","authors":"Taylor Holmes, Andrew Passerelli, J. Connor","doi":"10.1109/MTV.2015.11","DOIUrl":"https://doi.org/10.1109/MTV.2015.11","url":null,"abstract":"Our team has been developing a System on a Chip (SoC) and is using Synopsys VDK to accelerate both software development and hardware verification. We will discuss how VDK has helped us achieve our primary goal of starting software development and testing prior to design fabrication and our secondary goal of testing our RTL with software. The platform creation process and our transition from RTL-only to Transaction-Level-with-RTL co-simulations will be briefly discussed to provide background. We will also compare our efforts prototyping our design on FPGAs to our experience using VDK. The integration of VDK with an RTL simulator has provided a good balance of simulation speed and visibility down into the design and our engineers have been able to run design validation testing (DVT) software on a large portion of our final RTL prior to our tape out.","PeriodicalId":273432,"journal":{"name":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127779615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：