Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435705
S. Ravindran, C. Gautam, Aruna Tiwari
User Identification and User Verification are the primary problems in the area of Keystroke Dynamics. In the last decade there has been massive research in User Verification, and lesser research in User Identification. Both approaches take a username and a passphrase as input. In this paper, we introduce this problem of replacing authentication systems with the passphrase alone. This is done by using neural network based approach i.e. Extreme Learning Machine. ELM is a fast Single hidden layer feed forward network (SLFN) with good generalization performance. However the hidden layer in ELM does not have to be tuned. As an evolutionary step, we use a clustering based Semi-supervised approach (ECM-ELM) to User Recognition to combat variance in the accuracy of traditional ELMs. This research aims not only to address User Recognition problem but also to remove the instability in the accuracy of ELM. As per our simulation, ECM-ELM achieved a stable accuracy of 87% with the CMU Keystroke Dataset, while ELM achieved an unstable average accuracy of 90%.
{"title":"Keystroke user recognition through extreme learning machine and evolving cluster method","authors":"S. Ravindran, C. Gautam, Aruna Tiwari","doi":"10.1109/ICCIC.2015.7435705","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435705","url":null,"abstract":"User Identification and User Verification are the primary problems in the area of Keystroke Dynamics. In the last decade there has been massive research in User Verification, and lesser research in User Identification. Both approaches take a username and a passphrase as input. In this paper, we introduce this problem of replacing authentication systems with the passphrase alone. This is done by using neural network based approach i.e. Extreme Learning Machine. ELM is a fast Single hidden layer feed forward network (SLFN) with good generalization performance. However the hidden layer in ELM does not have to be tuned. As an evolutionary step, we use a clustering based Semi-supervised approach (ECM-ELM) to User Recognition to combat variance in the accuracy of traditional ELMs. This research aims not only to address User Recognition problem but also to remove the instability in the accuracy of ELM. As per our simulation, ECM-ELM achieved a stable accuracy of 87% with the CMU Keystroke Dataset, while ELM achieved an unstable average accuracy of 90%.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"96 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131771350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435750
P. Sreelakshmi, Kirti S. Pande, N. S. Murty
In this paper, a Modified Differential 8T SRAM cell is proposed for subthreshold region of operation. Forward Body biasing technique is used to improve the drivability of transistors and sleep transistor logic is used to reduce the leakage current in standby mode. The proposed design is implemented with 45 nm CMOS technology and is simulated using Cadence Virtuoso Simulator. At 0.5 V supply voltage, the read SNM and write SNM are 98 mV and 112 mV respectively and these are 32% and 21% higher than there reported in literature. The leakage current and power consumption of the cell are 3.26 fA and 1.63 fW respectively.
{"title":"SRAM cell with improved stability and reduced leakage current for subthreshold region of operation","authors":"P. Sreelakshmi, Kirti S. Pande, N. S. Murty","doi":"10.1109/ICCIC.2015.7435750","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435750","url":null,"abstract":"In this paper, a Modified Differential 8T SRAM cell is proposed for subthreshold region of operation. Forward Body biasing technique is used to improve the drivability of transistors and sleep transistor logic is used to reduce the leakage current in standby mode. The proposed design is implemented with 45 nm CMOS technology and is simulated using Cadence Virtuoso Simulator. At 0.5 V supply voltage, the read SNM and write SNM are 98 mV and 112 mV respectively and these are 32% and 21% higher than there reported in literature. The leakage current and power consumption of the cell are 3.26 fA and 1.63 fW respectively.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116096329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435762
G. Saini, V. Ravi
Outlier detection has been attracting the data analysts in almost every domain for a long time now because their detection is very challenging. Outliers or novel cases need to be detected before any analysis is performed on data set. Depending upon the domain, outlier detection saves a lot of time, money or both. In this paper, we developed a novel outlier detection model using ensembling technique, in the paradigm of soft computing, which includes four algorithms, namely k-Reverse Nearest Neighbor (kRNN), Auto Associative Neural Network (AANN), Counter Propagation Auto Association Neural Network (CPAANN), and Generalized Regression Auto Association Neural network (GRAANN) as constituents. The ensemble takes the union of all the outliers found by the four techniques.
{"title":"Outlier detection via a soft computing hybrid","authors":"G. Saini, V. Ravi","doi":"10.1109/ICCIC.2015.7435762","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435762","url":null,"abstract":"Outlier detection has been attracting the data analysts in almost every domain for a long time now because their detection is very challenging. Outliers or novel cases need to be detected before any analysis is performed on data set. Depending upon the domain, outlier detection saves a lot of time, money or both. In this paper, we developed a novel outlier detection model using ensembling technique, in the paradigm of soft computing, which includes four algorithms, namely k-Reverse Nearest Neighbor (kRNN), Auto Associative Neural Network (AANN), Counter Propagation Auto Association Neural Network (CPAANN), and Generalized Regression Auto Association Neural network (GRAANN) as constituents. The ensemble takes the union of all the outliers found by the four techniques.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125144727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435687
L. Puneeth, N. S. Murty
In this paper, we propose an architecture for Optimized Digital De-Skew Buffer (ODDB) with improved duty cycle correction using modified edge combiner and interpolator. The transmission gate based edge combiner suffers from the problem of glitches during the setup time and overshoots and undershoots afterwards. Our NAND gate based modified edge combiner, along with the interpolator, removes the glitches, drastically reduces the overshoots and undershoots and improves the duty cycle correction to deliver stable 50% duty cycle clock. A latch based clock gating circuit is used to reduce the power consumption of the ODDB. Half Delay Line blocks are used to introduce the delay and are designed using Coarse Delay Units and Fine Delay lines. The architecture is simulated using Cadence NCSim and the clock is optimized for setup time, hold time and power consumption using the Cadence SoC Encounter. The ODDB is designed and implemented using 45 nm CMOS technology with 1.1 V power supply and is optimized for 500MHz operation. The power consumption and total cell area of the ODDB are 40.6 μW and 354.312 μm2 respectively. A 6% power saving is achieved at the cost of 14% area overhead by implementing clock gating feature in ODDB. The modified edge combiner and interpolator have also been implemented using 45nm FinFET technology (BSIM CMG) and power reduction of 19% and 45% respectively are achieved when compared to the 45nm CMOS implementation.
{"title":"Low power clock Optimized Digital De-Skew Buffer with improved duty cycle correction","authors":"L. Puneeth, N. S. Murty","doi":"10.1109/ICCIC.2015.7435687","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435687","url":null,"abstract":"In this paper, we propose an architecture for Optimized Digital De-Skew Buffer (ODDB) with improved duty cycle correction using modified edge combiner and interpolator. The transmission gate based edge combiner suffers from the problem of glitches during the setup time and overshoots and undershoots afterwards. Our NAND gate based modified edge combiner, along with the interpolator, removes the glitches, drastically reduces the overshoots and undershoots and improves the duty cycle correction to deliver stable 50% duty cycle clock. A latch based clock gating circuit is used to reduce the power consumption of the ODDB. Half Delay Line blocks are used to introduce the delay and are designed using Coarse Delay Units and Fine Delay lines. The architecture is simulated using Cadence NCSim and the clock is optimized for setup time, hold time and power consumption using the Cadence SoC Encounter. The ODDB is designed and implemented using 45 nm CMOS technology with 1.1 V power supply and is optimized for 500MHz operation. The power consumption and total cell area of the ODDB are 40.6 μW and 354.312 μm2 respectively. A 6% power saving is achieved at the cost of 14% area overhead by implementing clock gating feature in ODDB. The modified edge combiner and interpolator have also been implemented using 45nm FinFET technology (BSIM CMG) and power reduction of 19% and 45% respectively are achieved when compared to the 45nm CMOS implementation.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122100769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435763
S. Gupta, Abhishek Mathur
Underwater Wireless Sensor Networks are generally used to explore aquatic environment. In UWSN, discovering the region of sensor node is a major issue. Observed data is useful when sensor node is localized. There are various approaches present for locating the nodes in Wireless Sensor Network yet they are not as useful in UWSN. In this paper we have presented various approaches available for UWSN. In our proposed work we are organizing the sensor nodes in a fixed moving pattern so that the nodes move in a particular area, the pattern is organized in hexagon structure. Our results show that the implemented algorithm provides better results in terms of performance parameters.
{"title":"Modified spray and wait routing in under water acostic communication for sensor network","authors":"S. Gupta, Abhishek Mathur","doi":"10.1109/ICCIC.2015.7435763","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435763","url":null,"abstract":"Underwater Wireless Sensor Networks are generally used to explore aquatic environment. In UWSN, discovering the region of sensor node is a major issue. Observed data is useful when sensor node is localized. There are various approaches present for locating the nodes in Wireless Sensor Network yet they are not as useful in UWSN. In this paper we have presented various approaches available for UWSN. In our proposed work we are organizing the sensor nodes in a fixed moving pattern so that the nodes move in a particular area, the pattern is organized in hexagon structure. Our results show that the implemented algorithm provides better results in terms of performance parameters.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130467379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435672
M. S. Manshahia, M. Dave, S. Singh
Problem of Congestion in Wireless Sensor Network (WSN) is an area which draws attention of various researchers in recent years. The challenge lies in developing a model for routing which can find the optimized route on the basis of distance between source and destination and the residual energy of the node. Various models have been proposed and developed from time to time and their merits and demerits have been discussed. This paper shows an implementation of the Improved Bat Algorithm which is based on the echolocation of bats to control congestion in Wireless Sensor Networks at transport layer. Simulation results have shown that as the number of hops in the path of data transmission increases the Queue length is decreases. The Congestion in the network decreases as the packets are transferred through different routes rather than collecting on a single node. Two important factors such as network lifetime and throughput are also compared with CODA (Congestion Detection and Avoidance) and PSO (Particle Swarm Optimization) algorithm.
{"title":"Bio inspired congestion control mechanism for Wireless Sensor Networks","authors":"M. S. Manshahia, M. Dave, S. Singh","doi":"10.1109/ICCIC.2015.7435672","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435672","url":null,"abstract":"Problem of Congestion in Wireless Sensor Network (WSN) is an area which draws attention of various researchers in recent years. The challenge lies in developing a model for routing which can find the optimized route on the basis of distance between source and destination and the residual energy of the node. Various models have been proposed and developed from time to time and their merits and demerits have been discussed. This paper shows an implementation of the Improved Bat Algorithm which is based on the echolocation of bats to control congestion in Wireless Sensor Networks at transport layer. Simulation results have shown that as the number of hops in the path of data transmission increases the Queue length is decreases. The Congestion in the network decreases as the packets are transferred through different routes rather than collecting on a single node. Two important factors such as network lifetime and throughput are also compared with CODA (Congestion Detection and Avoidance) and PSO (Particle Swarm Optimization) algorithm.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129334561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435758
Avinash More, Sharad Wagh, Kedar Joshi
Wireless Sensor Networks (WSN's) recently has been proposed for several applications. WSN can be used for habitat and ecosystem monitoring, seismic monitoring, civil structure health monitoring and industrial process monitoring. Such applications may include stationary or mobile sensor nodes that can move in the intended area to achieve a certain objectives of networks. This paper presents the development of an experimental test-bed for real-world Habitat Monitoring System (HMS). Our system consists of stationary sensor nodes which are integrated with Wi-Fi network to acquire the remote physical environmental data. We have integrated temperature, humidity and light sensors in our Habitat Monitoring System for investigating the performance of our HMS test-bed. The proposed test-bed of Habitat Monitoring System (HMS) describes the data monitoring, data handling, data storing and database management system. However, by replacing the sensors the developed test-bed can also be used for air population, forest fire detection, health care monitoring and water quality monitoring.
{"title":"A test-bed for habitat monitoring system using Wi-Fi in Wireless Sensor Networks","authors":"Avinash More, Sharad Wagh, Kedar Joshi","doi":"10.1109/ICCIC.2015.7435758","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435758","url":null,"abstract":"Wireless Sensor Networks (WSN's) recently has been proposed for several applications. WSN can be used for habitat and ecosystem monitoring, seismic monitoring, civil structure health monitoring and industrial process monitoring. Such applications may include stationary or mobile sensor nodes that can move in the intended area to achieve a certain objectives of networks. This paper presents the development of an experimental test-bed for real-world Habitat Monitoring System (HMS). Our system consists of stationary sensor nodes which are integrated with Wi-Fi network to acquire the remote physical environmental data. We have integrated temperature, humidity and light sensors in our Habitat Monitoring System for investigating the performance of our HMS test-bed. The proposed test-bed of Habitat Monitoring System (HMS) describes the data monitoring, data handling, data storing and database management system. However, by replacing the sensors the developed test-bed can also be used for air population, forest fire detection, health care monitoring and water quality monitoring.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127263528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435657
T. Aswathi, P. Sathishkumar
All Digital Phase Locked Loops are widely used as clock generators in multiprocessor system on chips. An error detection system is crucial for such clock generators since it can be used to notify different processors to shut down so as to prevent the propagation of a faulty clock. In this work, an All Digital Phase Locked Loop with an improved input clock failure detector is presented. The All Digital Phase Locked Loop proposed in this paper is designed to operate from 61KHz to 42Mhz. A completely digital approach is used for the design. The design achieves lock in less than 5 reference cycles. The input clock fail detector circuit detects the loss of input signal and notifies the controller. Fault detection is possible at an early stage and hence, it takes only 2 Digitally Controlled Oscillator clock cycles for stuck at fault detection and 1 reference clock cycle for out of limit fault detection. Entire design is done in Verilog hardware description language and hence it is highly versatile. Synthesis is done using cadence RTL compiler.
{"title":"All digital phase locked loop with input clock fail detector","authors":"T. Aswathi, P. Sathishkumar","doi":"10.1109/ICCIC.2015.7435657","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435657","url":null,"abstract":"All Digital Phase Locked Loops are widely used as clock generators in multiprocessor system on chips. An error detection system is crucial for such clock generators since it can be used to notify different processors to shut down so as to prevent the propagation of a faulty clock. In this work, an All Digital Phase Locked Loop with an improved input clock failure detector is presented. The All Digital Phase Locked Loop proposed in this paper is designed to operate from 61KHz to 42Mhz. A completely digital approach is used for the design. The design achieves lock in less than 5 reference cycles. The input clock fail detector circuit detects the loss of input signal and notifies the controller. Fault detection is possible at an early stage and hence, it takes only 2 Digitally Controlled Oscillator clock cycles for stuck at fault detection and 1 reference clock cycle for out of limit fault detection. Entire design is done in Verilog hardware description language and hence it is highly versatile. Synthesis is done using cadence RTL compiler.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126756617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435765
Kshitij Tayal, V. Ravi
In this paper, we developed a Binary Particle Swarm Optimization (BPSO) based fuzzy association rule miner to generate fuzzy association rules from a transactional database by formulating a combinatorial global optimization problem, without pre-defining minimum support and confidence unlike other conventional association miners. Goodness of fuzzy association rules is measured by a fitness function viz., the product of support and confidence. So as to demonstrate the effectiveness of our method, we implemented it to phishing detection domain. Based on the goodness of the rules obtained, we infer that our proposed algorithm can be used as a sound alternative to the fuzzy apriori algorithm.
{"title":"Fuzzy association rule mining using binary particle swarm optimization: Application to cyber fraud analytics","authors":"Kshitij Tayal, V. Ravi","doi":"10.1109/ICCIC.2015.7435765","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435765","url":null,"abstract":"In this paper, we developed a Binary Particle Swarm Optimization (BPSO) based fuzzy association rule miner to generate fuzzy association rules from a transactional database by formulating a combinatorial global optimization problem, without pre-defining minimum support and confidence unlike other conventional association miners. Goodness of fuzzy association rules is measured by a fitness function viz., the product of support and confidence. So as to demonstrate the effectiveness of our method, we implemented it to phishing detection domain. Based on the goodness of the rules obtained, we infer that our proposed algorithm can be used as a sound alternative to the fuzzy apriori algorithm.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127671218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/ICCIC.2015.7435794
A. Reddy, A. Govardhan
The objective of Resource allocation for the Choice based Education System using Semantic Web is to propose an implementation model for an agent software which acts as a bridge between different educational services, content-oriented intelligence and their semantic interoperation. This paper analyzes and identifies techniques necessary to develop an automatic choice based educational system for next generation to overcome human intervention. The different educational services such as course registration, examination module, schedules the courses, assessment of student and assessment of faculty need to be automated. It means that our system adopts a learning mechanism and provides the content - oriented intelligence and more semantic interoperation between these services and content. The paper proposes semantic web is realistic technology that supports to achieve such kind of flexibility.
{"title":"Resource allocation for the Choice based Education System using Semantic Web","authors":"A. Reddy, A. Govardhan","doi":"10.1109/ICCIC.2015.7435794","DOIUrl":"https://doi.org/10.1109/ICCIC.2015.7435794","url":null,"abstract":"The objective of Resource allocation for the Choice based Education System using Semantic Web is to propose an implementation model for an agent software which acts as a bridge between different educational services, content-oriented intelligence and their semantic interoperation. This paper analyzes and identifies techniques necessary to develop an automatic choice based educational system for next generation to overcome human intervention. The different educational services such as course registration, examination module, schedules the courses, assessment of student and assessment of faculty need to be automated. It means that our system adopts a learning mechanism and provides the content - oriented intelligence and more semantic interoperation between these services and content. The paper proposes semantic web is realistic technology that supports to achieve such kind of flexibility.","PeriodicalId":276894,"journal":{"name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127825900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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