Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453856
Juan Deng, R. Brooks, J. Taiber
Extensible Access Control Markup Language is an OASIS ratified standard that defines and enforces control policies. XACML bases access control on static user or resource attributes, which fails for a large class of security policies. Security automata specify security policies that base decisions on changing user or resource states. This paper extends XACML to support security automata. We demonstrate the extended XACML on a location-aware application for connected vehicles. We analyze the security of the extended XACML system. We secure the system with TLS and verify the system security using the Failure Divergence Refinement (FDR) and Casper tools.
{"title":"Security automata integrated XACML and security validation","authors":"Juan Deng, R. Brooks, J. Taiber","doi":"10.1109/SECON.2010.5453856","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453856","url":null,"abstract":"Extensible Access Control Markup Language is an OASIS ratified standard that defines and enforces control policies. XACML bases access control on static user or resource attributes, which fails for a large class of security policies. Security automata specify security policies that base decisions on changing user or resource states. This paper extends XACML to support security automata. We demonstrate the extended XACML on a location-aware application for connected vehicles. We analyze the security of the extended XACML system. We secure the system with TLS and verify the system security using the Failure Divergence Refinement (FDR) and Casper tools.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127432071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453877
G. Franklin, Shanshan Yang
This paper describes an impedance matching monitor for use with power line carrier systems on high voltage transmission lines. The purpose of the monitor is to determine when an undesirable impedance mismatch between a carrier transmitter and its load occurs, and to provide an alarm when the condition occurs. The alarm output is based on a calibrated setpoint that corresponds to some given percent reflected power level, or reflection coefficient, as opposed to an actual calculation of percent reflected power or reflection coefficient for a given impedance mismatch. That is, the system is calibrated with known impedance that results in the reflection coefficient that yields the desired percent reflected power alarm point. The monitor developed consists of two key components, which are a directional coupler and a controller. The impedance matching monitor was successfully installed on a PLC system used with a directional comparison blocking protection scheme on a 115-kV line.
{"title":"Power line carrier impedance matching monitor","authors":"G. Franklin, Shanshan Yang","doi":"10.1109/SECON.2010.5453877","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453877","url":null,"abstract":"This paper describes an impedance matching monitor for use with power line carrier systems on high voltage transmission lines. The purpose of the monitor is to determine when an undesirable impedance mismatch between a carrier transmitter and its load occurs, and to provide an alarm when the condition occurs. The alarm output is based on a calibrated setpoint that corresponds to some given percent reflected power level, or reflection coefficient, as opposed to an actual calculation of percent reflected power or reflection coefficient for a given impedance mismatch. That is, the system is calibrated with known impedance that results in the reflection coefficient that yields the desired percent reflected power alarm point. The monitor developed consists of two key components, which are a directional coupler and a controller. The impedance matching monitor was successfully installed on a PLC system used with a directional comparison blocking protection scheme on a 115-kV line.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129181628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453845
T. Olivo
This paper is a guide to solving some introductory problems encountered when considering ultra capacitors as an energy storage solution for power electronics. The methods used here can be used by the engineer to find solutions for many other applications that can not be found with conventional calculus.
{"title":"Analysis of ultra capacitors as UPS energy storage devices","authors":"T. Olivo","doi":"10.1109/SECON.2010.5453845","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453845","url":null,"abstract":"This paper is a guide to solving some introductory problems encountered when considering ultra capacitors as an energy storage solution for power electronics. The methods used here can be used by the engineer to find solutions for many other applications that can not be found with conventional calculus.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134498663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453920
S. Russ, Viswakalyan Perepa, Silas Leavesly, Bret M. Webb
Demand for embedded environmental sensors is increasing. One of the key sensor capabilities is the ability to measure salinity. In addition to understanding the environment, a salinity measurement is needed to estimate water density and to convert pressure to estimates of water depth. This outlines a low-cost sensor that combines an H-bridge and digital potentiometer to make an AC resistance measurement suitable for measuring salinity.
{"title":"Novel low-cost salinity sensor for embedded environmental monitoring","authors":"S. Russ, Viswakalyan Perepa, Silas Leavesly, Bret M. Webb","doi":"10.1109/SECON.2010.5453920","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453920","url":null,"abstract":"Demand for embedded environmental sensors is increasing. One of the key sensor capabilities is the ability to measure salinity. In addition to understanding the environment, a salinity measurement is needed to estimate water density and to convert pressure to estimates of water depth. This outlines a low-cost sensor that combines an H-bridge and digital potentiometer to make an AC resistance measurement suitable for measuring salinity.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131819077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453819
Justin P. Mattimore, R. Groff, T. Burg, Matthew E. Pepper
A method for interfacing an HP26 ink-jet cartridge to a computing resource is presented. A general purpose interface will allow new and custom application of ink-jet printing technology. Drive characteristics of the HP26 cartridge are captured and a driver board subsequently developed that permits direct control of nozzle firing timing and properties. Reproduction of the drive signal and satisfactory ink deposition is validated. The application of ink-jet printing technology to bioprinting research is targeted in this work.
{"title":"A general purpose driver board for the HP26 ink-jet cartridge with applications to bioprinting","authors":"Justin P. Mattimore, R. Groff, T. Burg, Matthew E. Pepper","doi":"10.1109/SECON.2010.5453819","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453819","url":null,"abstract":"A method for interfacing an HP26 ink-jet cartridge to a computing resource is presented. A general purpose interface will allow new and custom application of ink-jet printing technology. Drive characteristics of the HP26 cartridge are captured and a driver board subsequently developed that permits direct control of nozzle firing timing and properties. Reproduction of the drive signal and satisfactory ink deposition is validated. The application of ink-jet printing technology to bioprinting research is targeted in this work.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129353221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453824
Daniel Bedard, M. Lim, R. Fowler, Allan Porterfield
We have developed PowerMon and PowerMon2, low-cost power monitoring devices that operate inside commodity computer systems, to analyze performance and power consumption tradeoffs in computer applications. Inserted between a system's power supply and motherboard, PowerMon monitors voltage and current on six DC rails and reports measurements at a rate of up to fifty samples per second through a USB interface, allowing monitoring by the target or a separate host. PowerMon2 has a smaller form factor that fits in a standard 3.5" hard drive bay, allowing it to be used in a 1U server chassis. It features a faster measurement rate of up to 1024 Hz on a single channel or 3072 Hz divided among multiple channels. PowerMon2 also adds two measurement channels for additional peripherals, such as disks and graphical processing units. The PowerMon devices have been used to resolve and highlight variations in power consumption and energy efficiency at the subsystem level during separate operating phases of scientific performance benchmarks, such as NAS BT and SP. The device parts cost is low enough to provision an entire cluster for power monitoring and adaptation. Complete schematics, board layouts, and source code for the PowerMon devices are available under a BSD-style open source license at ilab.renci.org/powermon.
{"title":"PowerMon: Fine-grained and integrated power monitoring for commodity computer systems","authors":"Daniel Bedard, M. Lim, R. Fowler, Allan Porterfield","doi":"10.1109/SECON.2010.5453824","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453824","url":null,"abstract":"We have developed PowerMon and PowerMon2, low-cost power monitoring devices that operate inside commodity computer systems, to analyze performance and power consumption tradeoffs in computer applications. Inserted between a system's power supply and motherboard, PowerMon monitors voltage and current on six DC rails and reports measurements at a rate of up to fifty samples per second through a USB interface, allowing monitoring by the target or a separate host. PowerMon2 has a smaller form factor that fits in a standard 3.5\" hard drive bay, allowing it to be used in a 1U server chassis. It features a faster measurement rate of up to 1024 Hz on a single channel or 3072 Hz divided among multiple channels. PowerMon2 also adds two measurement channels for additional peripherals, such as disks and graphical processing units. The PowerMon devices have been used to resolve and highlight variations in power consumption and energy efficiency at the subsystem level during separate operating phases of scientific performance benchmarks, such as NAS BT and SP. The device parts cost is low enough to provision an entire cluster for power monitoring and adaptation. Complete schematics, board layouts, and source code for the PowerMon devices are available under a BSD-style open source license at ilab.renci.org/powermon.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453854
J. A. Berlier, J. M. McCollum
In prototyping and design of embedded systems, selection of the smallest possible microcontroller necessary to meet system requirements while minimizing power consumption and design size is desirable. With the myriad of microcontrollers available on the market, selecting the ideal microcontroller is a non-trivial task. In this work, we address this problem through the implementation of a constraint satisfaction algorithm that will assist in microcontroller selection by matching design requirements to the capabilities of individual microcontroller pins.
{"title":"A constraint satisfaction algorithm for microcontroller selection and pin assignment","authors":"J. A. Berlier, J. M. McCollum","doi":"10.1109/SECON.2010.5453854","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453854","url":null,"abstract":"In prototyping and design of embedded systems, selection of the smallest possible microcontroller necessary to meet system requirements while minimizing power consumption and design size is desirable. With the myriad of microcontrollers available on the market, selecting the ideal microcontroller is a non-trivial task. In this work, we address this problem through the implementation of a constraint satisfaction algorithm that will assist in microcontroller selection by matching design requirements to the capabilities of individual microcontroller pins.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453829
H. Basher
The control of a class of linear uncertain dynamic systems having time delays in state and control is investigated. The plant and input matrices of the system contain uncertain elements. The only information available about the uncertain parameters is the bounding sets in which they lie. Under certain assumptions a nonlinear control law is developed which forces the plant output to track the output of a delay-free reference model. The tracking error does not asymptotically decrease to zero; instead the error is bounded. This bound can be made arbitrarily small. The application of the theory is illustrated providing computer simulation results.
{"title":"Model reference control of uncertain time-delay systems","authors":"H. Basher","doi":"10.1109/SECON.2010.5453829","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453829","url":null,"abstract":"The control of a class of linear uncertain dynamic systems having time delays in state and control is investigated. The plant and input matrices of the system contain uncertain elements. The only information available about the uncertain parameters is the bounding sets in which they lie. Under certain assumptions a nonlinear control law is developed which forces the plant output to track the output of a delay-free reference model. The tracking error does not asymptotically decrease to zero; instead the error is bounded. This bound can be made arbitrarily small. The application of the theory is illustrated providing computer simulation results.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126184747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453818
Bradley F. Dutton, L. Lerner, S. Vemula, C. Stroud
We describe a Built-in Self-Test (BIST) approach that was developed for the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs). The approach is unique when compared with previous work because the I/O buffers are tested separately from the other programmable logic in the I/O cells. The capabilities and limitations of system-level use of this I/O buffer BIST are discussed in conjunction with experimental results from the implementation and actual use of the approach in systems.
{"title":"On system-level use of BIST for programmable Input/Output buffers in FPGAs","authors":"Bradley F. Dutton, L. Lerner, S. Vemula, C. Stroud","doi":"10.1109/SECON.2010.5453818","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453818","url":null,"abstract":"We describe a Built-in Self-Test (BIST) approach that was developed for the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs). The approach is unique when compared with previous work because the I/O buffers are tested separately from the other programmable logic in the I/O cells. The capabilities and limitations of system-level use of this I/O buffer BIST are discussed in conjunction with experimental results from the implementation and actual use of the approach in systems.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128118536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/SECON.2010.5453859
Shravani Yerabati, Zhen Hu, O. Elkeelany
Global Positioning System (GPS) is a space-based global navigation satellite system [1]. It provides time and location information to users anywhere on Earth [1]. Nowadays, GPS is very useful not only for military applications but also for civil applications. GPS receivers are placed in any embedded system to continuously calculate current time and location information. Hence, real-time synchronous systems can be designed. This paper presents the design challenges and implementation issues of real-time GPS receiver based on GPS Receiver Board and Altera DE2 FPGA Board. The functionalities of real time system is to receive the data packets from GPS Receiver board continuously and to display the time and location information using Altera DE2 Board in real time mode. The designed system also accepts set-up of desired time, so that synchronous actions can be made. These actions will be only done once the GPS time matches the set-up time. Finally, the field trial demonstrates the successful operation of the real-time GPS receiver system.
{"title":"Real-time GPS receiver implemented using Altera FPGA Board","authors":"Shravani Yerabati, Zhen Hu, O. Elkeelany","doi":"10.1109/SECON.2010.5453859","DOIUrl":"https://doi.org/10.1109/SECON.2010.5453859","url":null,"abstract":"Global Positioning System (GPS) is a space-based global navigation satellite system [1]. It provides time and location information to users anywhere on Earth [1]. Nowadays, GPS is very useful not only for military applications but also for civil applications. GPS receivers are placed in any embedded system to continuously calculate current time and location information. Hence, real-time synchronous systems can be designed. This paper presents the design challenges and implementation issues of real-time GPS receiver based on GPS Receiver Board and Altera DE2 FPGA Board. The functionalities of real time system is to receive the data packets from GPS Receiver board continuously and to display the time and location information using Altera DE2 Board in real time mode. The designed system also accepts set-up of desired time, so that synchronous actions can be made. These actions will be only done once the GPS time matches the set-up time. Finally, the field trial demonstrates the successful operation of the real-time GPS receiver system.","PeriodicalId":286940,"journal":{"name":"Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127280712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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