Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345455
M. Yang, V. Chan, S. Ku, M. Ieong, L. Shi, K. Chan, C. Murthy, R. Mo, H.S. Yang, E. A. Lehner, Y. Surpris, F. Jamin, P. Oldiges, Y. Zhang, B. To, J. Holt, S. Steen, M. Chudzik, D. Fried, K. Bernstein, H. Zhu, C. Sung, J. Ott, D. Boyd, N. Rovedo
Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring oscillators using HOT CMOS have been demonstrated for the first time, with L/sub poly/ about 85nm and t/sub ox/=2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.
{"title":"On the integration of CMOS with hybrid crystal orientations","authors":"M. Yang, V. Chan, S. Ku, M. Ieong, L. Shi, K. Chan, C. Murthy, R. Mo, H.S. Yang, E. A. Lehner, Y. Surpris, F. Jamin, P. Oldiges, Y. Zhang, B. To, J. Holt, S. Steen, M. Chudzik, D. Fried, K. Bernstein, H. Zhu, C. Sung, J. Ott, D. Boyd, N. Rovedo","doi":"10.1109/VLSIT.2004.1345455","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345455","url":null,"abstract":"Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring oscillators using HOT CMOS have been demonstrated for the first time, with L/sub poly/ about 85nm and t/sub ox/=2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127082781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345368
F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, Augusto Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, Alberto Modelli, E. Varesi, T. Lowrey, A. L. Lacaita, G. Casagrande, P. Cappelletti, R. Bez
A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new /spl mu/trench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 /spl mu/A, endurance of 10/sup 11/ programming cycles and data retention capabilities for 10 years at 110/spl deg/C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.
{"title":"Novel /spl mu/trench phase-change memory cell for embedded and stand-alone non-volatile memory applications","authors":"F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, Augusto Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, Alberto Modelli, E. Varesi, T. Lowrey, A. L. Lacaita, G. Casagrande, P. Cappelletti, R. Bez","doi":"10.1109/VLSIT.2004.1345368","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345368","url":null,"abstract":"A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new /spl mu/trench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 /spl mu/A, endurance of 10/sup 11/ programming cycles and data retention capabilities for 10 years at 110/spl deg/C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127211942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345400
D. Lee, F. Tsui, Jeng-Wei Yang, F. Gao, Wen-Juei Lu, Yeeheng Lee, Chi-Tsai Chen, V. Huang, Pin-Yao Wang, M. Liu, H. Hsu, S. Chang, S.Y. Chang, H. van Tran, J. Frayer, Yaw-Wen Hu, B. Yeh, B. Chen
We present the structural and electrical characteristics of the latest generation of a self-aligned split-gate NOR memory incorporating a vertical floating-gate channel having 4.5F/sup 2/ area on 110 nm half-pitch rules. With enhanced electric fields for erase and programming, the cell achieves erase time < 1 ms and program time < 10 /spl mu/s at 100nA programming current. These results demonstrate continued scalability of the SuperFlash cell for high-density, high-speed applications.
{"title":"Vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory at 110nm node","authors":"D. Lee, F. Tsui, Jeng-Wei Yang, F. Gao, Wen-Juei Lu, Yeeheng Lee, Chi-Tsai Chen, V. Huang, Pin-Yao Wang, M. Liu, H. Hsu, S. Chang, S.Y. Chang, H. van Tran, J. Frayer, Yaw-Wen Hu, B. Yeh, B. Chen","doi":"10.1109/VLSIT.2004.1345400","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345400","url":null,"abstract":"We present the structural and electrical characteristics of the latest generation of a self-aligned split-gate NOR memory incorporating a vertical floating-gate channel having 4.5F/sup 2/ area on 110 nm half-pitch rules. With enhanced electric fields for erase and programming, the cell achieves erase time < 1 ms and program time < 10 /spl mu/s at 100nA programming current. These results demonstrate continued scalability of the SuperFlash cell for high-density, high-speed applications.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125293822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345459
A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, J. Koga
A novel approach for achieving high-performance Schottky-source/drain MOSFETs (SBTs: Schottky Barrier Transistors) is proposed. The dopant segregation (DS) technique is employed and significant modulation of Schottky barrier height is demonstrated. The DS-SBT fabricated with the current CoSi/sub 2/ process show competitive drive current and better short-channel-effect immunity compared to the conventional MOSFET. In conclusion the DS-Schottky junction is useful for the source/drain of advanced MOSFETs.
{"title":"Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique","authors":"A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, J. Koga","doi":"10.1109/VLSIT.2004.1345459","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345459","url":null,"abstract":"A novel approach for achieving high-performance Schottky-source/drain MOSFETs (SBTs: Schottky Barrier Transistors) is proposed. The dopant segregation (DS) technique is employed and significant modulation of Schottky barrier height is demonstrated. The DS-SBT fabricated with the current CoSi/sub 2/ process show competitive drive current and better short-channel-effect immunity compared to the conventional MOSFET. In conclusion the DS-Schottky junction is useful for the source/drain of advanced MOSFETs.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122314232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345485
M. Houssa, S. Gendt, J. Autran, Guido Groeseneken, M. Heyns
The impact of hydrogen on negative bias temperature instabilities (NBTI) in atomic layer deposited (ALD) HfO/sub 2/-based pMOSFETs is reported for the first time. After forming gas anneal (FGA) at high temperature (580/spl deg/C), the saturated threshold voltage (V/sub th/) shift of the devices is about 100 mV at 125/spl deg/C and V/sub G/ = -1.5 V. The V/sub th/ instability is reduced to about 50 mV for devices annealed in forming gas at 520/spl deg/C. Detailed analysis of the experimental results indicates that the defects responsible for NBTI are hydrogen-induced overcoordinated oxygen centers, induced by the transport and trapping of H/sup +/ in the gate stack. The V/sub th/ shift can be further reduced to less than 5 mV after subjecting the transistors to a higher thermal budget during the dopant activation anneal, which allows to release the strain at the Si/dielectric interface as well as to drive hydrogen out of the high-k gate stack. This finding is very important with respect to the thermal budget requirements for scaled CMOS processes.
{"title":"Detrimental impact of hydrogen on negative bias temperature instabilities in HfO/sub 2/-based pMOSFETs","authors":"M. Houssa, S. Gendt, J. Autran, Guido Groeseneken, M. Heyns","doi":"10.1109/VLSIT.2004.1345485","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345485","url":null,"abstract":"The impact of hydrogen on negative bias temperature instabilities (NBTI) in atomic layer deposited (ALD) HfO/sub 2/-based pMOSFETs is reported for the first time. After forming gas anneal (FGA) at high temperature (580/spl deg/C), the saturated threshold voltage (V/sub th/) shift of the devices is about 100 mV at 125/spl deg/C and V/sub G/ = -1.5 V. The V/sub th/ instability is reduced to about 50 mV for devices annealed in forming gas at 520/spl deg/C. Detailed analysis of the experimental results indicates that the defects responsible for NBTI are hydrogen-induced overcoordinated oxygen centers, induced by the transport and trapping of H/sup +/ in the gate stack. The V/sub th/ shift can be further reduced to less than 5 mV after subjecting the transistors to a higher thermal budget during the dopant activation anneal, which allows to release the strain at the Si/dielectric interface as well as to drive hydrogen out of the high-k gate stack. This finding is very important with respect to the thermal budget requirements for scaled CMOS processes.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"60 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114116706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345387
K. Mistry, M. Armstrong, P. AuthChristopher, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, Kevin Zhang, S. Thompson, M. Bohr
We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.
{"title":"Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology","authors":"K. Mistry, M. Armstrong, P. AuthChristopher, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, Kevin Zhang, S. Thompson, M. Bohr","doi":"10.1109/VLSIT.2004.1345387","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345387","url":null,"abstract":"We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115930076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345480
H. Shang, J. Chu, X. Wang, P. Mooney, K. Lee, J. Ott, K. Rim, K. Chan, K. Guarini, M. Ieong
In this work, the channel design space for scaled strained Ge (s-Ge) buried channel (BC) MOSFETs is examined by simulations and experiments. The identified Ge channel layer structure is scalable to sub-30nm devices. Furthermore, strained Ge buried-channel MOSFETs with an ultra thin (1.5nm) Si cap are demonstrated with a 6/spl times/ hole mobility enhancement over the Si universal hole mobility. Compared with surface channel Ge MOSFETs. buried strained Ge channel structures can be integrated with fewer processing challenges to achieve a significantly enhanced hole mobility and an improved electron mobility.
{"title":"Channel design and mobility enhancement in strained germanium buried channel MOSFETs","authors":"H. Shang, J. Chu, X. Wang, P. Mooney, K. Lee, J. Ott, K. Rim, K. Chan, K. Guarini, M. Ieong","doi":"10.1109/VLSIT.2004.1345480","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345480","url":null,"abstract":"In this work, the channel design space for scaled strained Ge (s-Ge) buried channel (BC) MOSFETs is examined by simulations and experiments. The identified Ge channel layer structure is scalable to sub-30nm devices. Furthermore, strained Ge buried-channel MOSFETs with an ultra thin (1.5nm) Si cap are demonstrated with a 6/spl times/ hole mobility enhancement over the Si universal hole mobility. Compared with surface channel Ge MOSFETs. buried strained Ge channel structures can be integrated with fewer processing challenges to achieve a significantly enhanced hole mobility and an improved electron mobility.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130108546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345429
L. Pantisano, P. Chen, V. Afanas’ev, L. Ragnarsson, G. Pourtois, G. Groeseneken
In this study comprehensive experimental measurements together with a physical picture demonstrate that, regardless of poly-Si doping, the defects creation in the dielectric close to the poly-Si/HfO/sub 2/ interface is responsible for the observed effective WF change. These defects are amphoteric and spatially nonuniformly distributed.
{"title":"Direct measurement of barrier height at the HfO/sub 2//poly-Si interface: Band structure and local effects","authors":"L. Pantisano, P. Chen, V. Afanas’ev, L. Ragnarsson, G. Pourtois, G. Groeseneken","doi":"10.1109/VLSIT.2004.1345429","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345429","url":null,"abstract":"In this study comprehensive experimental measurements together with a physical picture demonstrate that, regardless of poly-Si doping, the defects creation in the dielectric close to the poly-Si/HfO/sub 2/ interface is responsible for the observed effective WF change. These defects are amphoteric and spatially nonuniformly distributed.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128954524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345409
M. Togo, T. Fukai, Y. Nakahara, S. Koyama, M. Makabe, E. Hasegawa, M. Nagase, T. Matsuda, K. Sakamoto, S. Fujiwara, Y. Goto, T. Yamamoto, T. Mogami, M. Ikeda, Y. Yamagata, K. Imai
We have developed a power-aware CMOS technology featuring variable V/sub DD/ and back-bias control. Three typical operation modes are defined: high-speed mode (V/sub DD/ = 1.2V, V/sub B/ = 0V), nominal mode (V/sub DD/ = 0.9V, V/sub B/ = -0.5V) and power-save mode (V/sub DD/ = 0.6V, V/sub B/ = -2.0V). Compared with nominal mode, one and a half order of magnitude reduction of standby leakage current is achieved with power-save mode, while 75% higher drivability is achieved with high-speed mode. Device reliability for back-bias condition was also investigated. With higher back-bias, NBT (Negative Bias Temperature) degradation for pFET is enhanced especially in the case of thinner gate oxide. From activation energy, we believe the dominant mechanism is SHH (Substrate Hot-Hole) injection. Reduced V/sub DD/ at standby mode drastically alleviates this degradation caused by NBT stress and SHH injection. With appropriate V/sub DD/ and V/sub B/ combination, power-aware 65nm CMOS with sufficient reliability can be achieved.
{"title":"Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode","authors":"M. Togo, T. Fukai, Y. Nakahara, S. Koyama, M. Makabe, E. Hasegawa, M. Nagase, T. Matsuda, K. Sakamoto, S. Fujiwara, Y. Goto, T. Yamamoto, T. Mogami, M. Ikeda, Y. Yamagata, K. Imai","doi":"10.1109/VLSIT.2004.1345409","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345409","url":null,"abstract":"We have developed a power-aware CMOS technology featuring variable V/sub DD/ and back-bias control. Three typical operation modes are defined: high-speed mode (V/sub DD/ = 1.2V, V/sub B/ = 0V), nominal mode (V/sub DD/ = 0.9V, V/sub B/ = -0.5V) and power-save mode (V/sub DD/ = 0.6V, V/sub B/ = -2.0V). Compared with nominal mode, one and a half order of magnitude reduction of standby leakage current is achieved with power-save mode, while 75% higher drivability is achieved with high-speed mode. Device reliability for back-bias condition was also investigated. With higher back-bias, NBT (Negative Bias Temperature) degradation for pFET is enhanced especially in the case of thinner gate oxide. From activation energy, we believe the dominant mechanism is SHH (Substrate Hot-Hole) injection. Reduced V/sub DD/ at standby mode drastically alleviates this degradation caused by NBT stress and SHH injection. With appropriate V/sub DD/ and V/sub B/ combination, power-aware 65nm CMOS with sufficient reliability can be achieved.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131425654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-15DOI: 10.1109/VLSIT.2004.1345416
W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linten, S. Thijs, S. Jenei, C. Detcheverry, P. Wambacq, R. Velghe, S. Decoutere
The potential for low power RF systems on chip of a 90nm CMOS technology is demonstrated for the first time on a monolithic 5GHz low noise amplifier. This technology combines a portfolio of high Q passive components with high RF performances 70nm physical gate length NMOSFETs (200GHz f/sub max/ -150GHz f/sub T/) presenting a ratio power gain/current gain higher than 1 up to the maximum measurement frequency.
{"title":"Integration of a 90nm RF CMOS technology (200GHz f/sub max/ - 150GHz f/sub T/ NMOS) demonstrated on a 5GHz LNA","authors":"W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linten, S. Thijs, S. Jenei, C. Detcheverry, P. Wambacq, R. Velghe, S. Decoutere","doi":"10.1109/VLSIT.2004.1345416","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345416","url":null,"abstract":"The potential for low power RF systems on chip of a 90nm CMOS technology is demonstrated for the first time on a monolithic 5GHz low noise amplifier. This technology combines a portfolio of high Q passive components with high RF performances 70nm physical gate length NMOSFETs (200GHz f/sub max/ -150GHz f/sub T/) presenting a ratio power gain/current gain higher than 1 up to the maximum measurement frequency.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124346834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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