Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509624
Mian Dong, Po-Hsiang Lai, Zhu Li
Power trace of a smartphone, as time series data, carries important information of the system behavior and is useful for many applications, such as energy management [1-3], software optimization [4-6] and anomaly detection [7, 8]. However, the power trace measured from the battery terminals include the power consumption by all the hardware components and thus describes the activity of the whole system. Yet modern smartphones are multiprocessing, i.e., multiple applications can be running simultaneously in the same system. Our goal is to answer the following question: “Can we identify smartphone app by power trace?” That is, whether the power trace of a smartphone can be different by running different applications.
{"title":"Can we identify smartphone app by power trace? [Extended abstract for special session]","authors":"Mian Dong, Po-Hsiang Lai, Zhu Li","doi":"10.1109/ASPDAC.2013.6509624","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509624","url":null,"abstract":"Power trace of a smartphone, as time series data, carries important information of the system behavior and is useful for many applications, such as energy management [1-3], software optimization [4-6] and anomaly detection [7, 8]. However, the power trace measured from the battery terminals include the power consumption by all the hardware components and thus describes the activity of the whole system. Yet modern smartphones are multiprocessing, i.e., multiple applications can be running simultaneously in the same system. Our goal is to answer the following question: “Can we identify smartphone app by power trace?” That is, whether the power trace of a smartphone can be different by running different applications.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"9 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131806343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509653
Yuki Yoshikawa
A binding method in high-level synthesis for path delay testability is proposed in this paper. For a given scheduled data flow graph, the proposed method synthesizes a path delay testable RTL datapath and its controller. Every path in the datapath is two pattern testable with the controller if the path is activated in the functional operation, i.e., the path is not false path. Our experimental results show that the proposed method can synthesize such RTL circuits with small area overhead compared with that augmented by some DFT techniques such as scan design.
{"title":"A binding algorithm in high-level synthesis for path delay testability","authors":"Yuki Yoshikawa","doi":"10.1109/ASPDAC.2013.6509653","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509653","url":null,"abstract":"A binding method in high-level synthesis for path delay testability is proposed in this paper. For a given scheduled data flow graph, the proposed method synthesizes a path delay testable RTL datapath and its controller. Every path in the datapath is two pattern testable with the controller if the path is activated in the functional operation, i.e., the path is not false path. Our experimental results show that the proposed method can synthesize such RTL circuits with small area overhead compared with that augmented by some DFT techniques such as scan design.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130308657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509611
Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen
As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system designs. Also, the conventional bottom-up design method incurs costly iterations in the STT-RAM design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven top-down design method to explore the design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a top-down design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early design stage of memory or micro-architecture by eliminating the design integrations, while offering a full statistical view of the design even when the common yield enhancement practices are applied.
{"title":"Loadsa: A yield-driven top-down design method for STT-RAM array","authors":"Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen","doi":"10.1109/ASPDAC.2013.6509611","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509611","url":null,"abstract":"As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system designs. Also, the conventional bottom-up design method incurs costly iterations in the STT-RAM design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven top-down design method to explore the design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a top-down design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early design stage of memory or micro-architecture by eliminating the design integrations, while offering a full statistical view of the design even when the common yield enhancement practices are applied.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129383959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Developing FPGA solutions for streaming applications written in C (or its variants) can benefit greatly from automatic C-to-RTL (C2RTL) synthesis. Yet, the complexity and stringent throughput/cost constraints of such applications are rather challenging for existing C2RTL synthesis tools. This paper considers automatic partition and block-level parallelization to address these challenges. An MILP-based approach is introduced for finding an optimal partition of a given program into blocks while allowing block-level parallelization. In order to handle extremely large problem instances, a heuristic algorithm is also discussed. Experimental results based on seven well known multimedia applications demonstrate the effectiveness of both solutions.
{"title":"Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications","authors":"Shuangchen Li, Yongpan Liu, X. Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang","doi":"10.1109/ASPDAC.2013.6509600","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509600","url":null,"abstract":"Developing FPGA solutions for streaming applications written in C (or its variants) can benefit greatly from automatic C-to-RTL (C2RTL) synthesis. Yet, the complexity and stringent throughput/cost constraints of such applications are rather challenging for existing C2RTL synthesis tools. This paper considers automatic partition and block-level parallelization to address these challenges. An MILP-based approach is introduced for finding an optimal partition of a given program into blocks while allowing block-level parallelization. In order to handle extremely large problem instances, a heuristic algorithm is also discussed. Experimental results based on seven well known multimedia applications demonstrate the effectiveness of both solutions.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116851251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509669
Ting-Shuo Chou, T. Givargis, Chen-Chun Huang, Bailey Miller, F. Vahid
This paper outlines a transparent and nonintrusive checkpointing mechanism for use with FPGA-based digital mockups. A digital mockup is an executable model of a physical system and used for real-time test and validation of cyber-physical devices that interact with the physical system. These digital mockups are typically defined in terms of a large set of ordinary differential equations. We consider digital mockups impelemented on field-programmable gate arrays (FPGAs). A checkpoint is a snapshot of the internal state of the model at a specific point in time as captured by some controller that resides on the same FPGA. We require that the model continues uninterrupted execution during a checkpointing operation. Once a checkpoint is created, the corresponding state information is transferred from the FPGA to a host computer for visualization and other off-chip processing. We outline the architecture of a checkpointing controller that captures and transfers the state information at a desired clock cycle using an aggressive compression technique. Our compression technique achieves 90% reduction in data transferred from the FPGA to the host computer under periodic checkpointing scenarios. The checkpointing with compression yields 15-36% FPGA size overhead, versus 6-11% for checkpointing without compression.
{"title":"An efficient compression scheme for checkpointing of FPGA-based digital mockups","authors":"Ting-Shuo Chou, T. Givargis, Chen-Chun Huang, Bailey Miller, F. Vahid","doi":"10.1109/ASPDAC.2013.6509669","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509669","url":null,"abstract":"This paper outlines a transparent and nonintrusive checkpointing mechanism for use with FPGA-based digital mockups. A digital mockup is an executable model of a physical system and used for real-time test and validation of cyber-physical devices that interact with the physical system. These digital mockups are typically defined in terms of a large set of ordinary differential equations. We consider digital mockups impelemented on field-programmable gate arrays (FPGAs). A checkpoint is a snapshot of the internal state of the model at a specific point in time as captured by some controller that resides on the same FPGA. We require that the model continues uninterrupted execution during a checkpointing operation. Once a checkpoint is created, the corresponding state information is transferred from the FPGA to a host computer for visualization and other off-chip processing. We outline the architecture of a checkpointing controller that captures and transfers the state information at a desired clock cycle using an aggressive compression technique. Our compression technique achieves 90% reduction in data transferred from the FPGA to the host computer under periodic checkpointing scenarios. The checkpointing with compression yields 15-36% FPGA size overhead, versus 6-11% for checkpointing without compression.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114580027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509626
Kent W. Nixon, Xiang Chen, Zhihong Mao, Yiran Chen, Kang Li
Intelligent mobile devices have been widely serving in almost all aspects of everyday life, spanning from communication, web surfing, entertainment, to daily organizer. A large amount of sensitive and private information is stored on the mobile device, leading to severe data security concern. In this work, we propose a novel mobile user classification and authorization scheme based on the recognition of user's gesture. Compared to other security solutions like password, track pattern and finger print etc., our scheme can continuously evolve for better protection during the usage cycle of the mobile device. Besides the regular interactive screen and sensors of modern mobile devices, our scheme does not require any additional hardware supports.
{"title":"Mobile user classification and authorization based on gesture usage recognition","authors":"Kent W. Nixon, Xiang Chen, Zhihong Mao, Yiran Chen, Kang Li","doi":"10.1109/ASPDAC.2013.6509626","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509626","url":null,"abstract":"Intelligent mobile devices have been widely serving in almost all aspects of everyday life, spanning from communication, web surfing, entertainment, to daily organizer. A large amount of sensitive and private information is stored on the mobile device, leading to severe data security concern. In this work, we propose a novel mobile user classification and authorization scheme based on the recognition of user's gesture. Compared to other security solutions like password, track pattern and finger print etc., our scheme can continuously evolve for better protection during the usage cycle of the mobile device. Besides the regular interactive screen and sensors of modern mobile devices, our scheme does not require any additional hardware supports.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122741727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509677
Keitarou Oka, Hiroshi Sasaki, Koji Inoue
This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of cache misses without increasing the size of the cache memory. It stores lines which contain the identical value in a single line entry, which enables to store greater amount of lines. Evaluation results show performance improvements of up to 35% across a set of SPEC CPU2000 benchmarks.
{"title":"Line sharing cache: Exploring cache capacity with frequent line value locality","authors":"Keitarou Oka, Hiroshi Sasaki, Koji Inoue","doi":"10.1109/ASPDAC.2013.6509677","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509677","url":null,"abstract":"This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of cache misses without increasing the size of the cache memory. It stores lines which contain the identical value in a single line entry, which enables to store greater amount of lines. Evaluation results show performance improvements of up to 35% across a set of SPEC CPU2000 benchmarks.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121537304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509549
A. Engin
Parasitic RC behavior of VLSI interconnects has been the major bottleneck in terms of latency and power consumption of ICs. Recent 3D ICs promise to reduce the parasitic RC effect by making use of through silicon vias (TSVs). It is therefore essential to extract the RC model of TSVs to assess their promise. Unlike interconnects on metal layers, TSVs exhibit slow-wave and dielectric quasi-transverse-electromagnetic (TEM) modes due to the coupling to the semiconducting substrate. This TSV behavior can be simulated using analytical methods, 2D electrostatic simulators, or 3D full-wave electromagnetic simulators. In this paper, we describe a methodology to extract parasitic RC models from such simulation data for interconnects in a 3D IC.
{"title":"Equivalent circuit model extraction for interconnects in 3D ICs","authors":"A. Engin","doi":"10.1109/ASPDAC.2013.6509549","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509549","url":null,"abstract":"Parasitic RC behavior of VLSI interconnects has been the major bottleneck in terms of latency and power consumption of ICs. Recent 3D ICs promise to reduce the parasitic RC effect by making use of through silicon vias (TSVs). It is therefore essential to extract the RC model of TSVs to assess their promise. Unlike interconnects on metal layers, TSVs exhibit slow-wave and dielectric quasi-transverse-electromagnetic (TEM) modes due to the coupling to the semiconducting substrate. This TSV behavior can be simulated using analytical methods, 2D electrostatic simulators, or 3D full-wave electromagnetic simulators. In this paper, we describe a methodology to extract parasitic RC models from such simulation data for interconnects in a 3D IC.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130367473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509635
Kai-Chung Chan, Chao-Jam Hsu, Jiarping Lin
This paper presents a new flow to handle fixed-outline floorplanning for mixed size modules. It consists of two stages, which include global distribution stage and legalization stage. The methodology is very flexible, which can be integrated into other methods or be extended to handle other constraints such as routability or thermal issue. The global distribution stage aims to obtain better wirelength while distributing modules over a fixed outline. Once a good result can be obtained in the first stage, the legalization stage only needs to obtain a feasible solution by maintaining the good result. The legalization is performed by curve merging in a slicing tree, which is obtained by the partition based approach. Two functions are proposed to divide a circuit and the associated placement region into two parts. Although the fixed-outline floorplanning with mixed size modules is very difficult, our method still can obtain better results. The experimental results show that our method can averagely reduce wirelength by 22.5% and 4.7% than PATOMA [1] and DeFer [2] in mixed size benchmarks.
{"title":"A flexible fixed-outline floorplanning methodology for mixed-size modules","authors":"Kai-Chung Chan, Chao-Jam Hsu, Jiarping Lin","doi":"10.1109/ASPDAC.2013.6509635","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509635","url":null,"abstract":"This paper presents a new flow to handle fixed-outline floorplanning for mixed size modules. It consists of two stages, which include global distribution stage and legalization stage. The methodology is very flexible, which can be integrated into other methods or be extended to handle other constraints such as routability or thermal issue. The global distribution stage aims to obtain better wirelength while distributing modules over a fixed outline. Once a good result can be obtained in the first stage, the legalization stage only needs to obtain a feasible solution by maintaining the good result. The legalization is performed by curve merging in a slicing tree, which is obtained by the partition based approach. Two functions are proposed to divide a circuit and the associated placement region into two parts. Although the fixed-outline floorplanning with mixed size modules is very difficult, our method still can obtain better results. The experimental results show that our method can averagely reduce wirelength by 22.5% and 4.7% than PATOMA [1] and DeFer [2] in mixed size benchmarks.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133153036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/ASPDAC.2013.6509570
Junyoung Song, Hyun-Woo Lee, Sewook Hwang, I. Jung, Chulwoo Kim
A 7.5Gb/s referenceless transceiver for the ultra-high definition television is designed in a 0.13μm CMOS process. By applying the dynamic pre-emphasis calibration and the bandwidth scanning clock generators, measured eye opening and jitter of the clock are enhanced by 39.6% and 40%, respectively. Also the data-width comparison based adaptive equalizer with self-adjusting reference voltage is proposed.
{"title":"A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process","authors":"Junyoung Song, Hyun-Woo Lee, Sewook Hwang, I. Jung, Chulwoo Kim","doi":"10.1109/ASPDAC.2013.6509570","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509570","url":null,"abstract":"A 7.5Gb/s referenceless transceiver for the ultra-high definition television is designed in a 0.13μm CMOS process. By applying the dynamic pre-emphasis calibration and the bandwidth scanning clock generators, measured eye opening and jitter of the clock are enhanced by 39.6% and 40%, respectively. Also the data-width comparison based adaptive equalizer with self-adjusting reference voltage is proposed.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134383538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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