This paper proposes a method for the derivation of end-to-end delays of applications that involve processing on multiple components in a heterogeneous multiprocessor system. The rocedure precisely captures the pipelined and parallel processing of multiple events along an application path by accurately capturing the resource timing and avoiding the pay-bursts-only-once problem. Both time-triggered and event-triggered task activation schemes with arbitrary event patterns are supported. In contrast to previous work, complex application topologies are allowed: The approach considers path forking and merging, as well as functional cycles and non-functional cyclic dependencies. The basis for the proposed method is an iterative compositional performance analysis, that allows computing event models in such systems. Based on the event models and local performance abstractions we propose a recursive approach to the derivation of the worst-case latency.
{"title":"A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems","authors":"S. Schliecker, R. Ernst","doi":"10.1145/1629435.1629494","DOIUrl":"https://doi.org/10.1145/1629435.1629494","url":null,"abstract":"This paper proposes a method for the derivation of end-to-end delays of applications that involve processing on multiple components in a heterogeneous multiprocessor system. The rocedure precisely captures the pipelined and parallel processing of multiple events along an application path by accurately capturing the resource timing and avoiding the pay-bursts-only-once problem. Both time-triggered and event-triggered task activation schemes with arbitrary event patterns are supported. In contrast to previous work, complex application topologies are allowed: The approach considers path forking and merging, as well as functional cycles and non-functional cyclic dependencies. The basis for the proposed method is an iterative compositional performance analysis, that allows computing event models in such systems. Based on the event models and local performance abstractions we propose a recursive approach to the derivation of the worst-case latency.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Energy-aware design for electronic systems has been an important issue in hardware and software implementations. Dynamic voltage scaling (DVS) techniques have been adopted to effectively trade the performance for the energy consumption. However, most existing research for energy-efficient design in DVS systems with realtime constraints focuses on tasks with worst-case execution times. Once a task instance completes earlier than its worst-case estimation, the unused slacks can be used for slowing down to reduce the energy consumption. This paper explores how to efficiently and effectively minimize the energy consumption to schedule a set of periodic real-time tasks with the multiframe property, in which the execution times of task instances are characterized by a vector of elements that are repeated. This paper proposes two types of approaches: (1) the task-based approach and (2) the frame-based approach. The task-based approach allocates the same time length for the executions of task instances belonging to the same task. The frame-based approach can reduce the energy consumption further by assigning an execution speed to each task frame. For on-line use, the scheduling overhead for speed determination is constant in both types of the proposed approaches. Simulations show that our proposed approaches sacrifice some optimality in terms of energy savings, compared to the optimal solutions, but require less space and less overhead for scheduling in the on-line (run-time) fashion.
{"title":"Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processor","authors":"Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo","doi":"10.1145/1629435.1629465","DOIUrl":"https://doi.org/10.1145/1629435.1629465","url":null,"abstract":"Energy-aware design for electronic systems has been an important issue in hardware and software implementations. Dynamic voltage scaling (DVS) techniques have been adopted to effectively trade the performance for the energy consumption. However, most existing research for energy-efficient design in DVS systems with realtime constraints focuses on tasks with worst-case execution times. Once a task instance completes earlier than its worst-case estimation, the unused slacks can be used for slowing down to reduce the energy consumption. This paper explores how to efficiently and effectively minimize the energy consumption to schedule a set of periodic real-time tasks with the multiframe property, in which the execution times of task instances are characterized by a vector of elements that are repeated. This paper proposes two types of approaches: (1) the task-based approach and (2) the frame-based approach. The task-based approach allocates the same time length for the executions of task instances belonging to the same task. The frame-based approach can reduce the energy consumption further by assigning an execution speed to each task frame. For on-line use, the scheduling overhead for speed determination is constant in both types of the proposed approaches. Simulations show that our proposed approaches sacrifice some optimality in terms of energy savings, compared to the optimal solutions, but require less space and less overhead for scheduling in the on-line (run-time) fashion.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126726365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Streaming applications can be implemented with a pipeline of processors. Each processor in the pipeline can be an application Specific Instruction Set Processor (ASIP) with the result being a heterogeneous pipelined MPSoC system. Since ASIPs can be of differing configurations, finding the optimal set of configurations for a multiprocessor architecture is a difficult problem. In this paper, we obtain an optimal system design for a set of processors which execute a multimedia application. The variables in the system are the presence or absence of different additional instructions and differing cache configurations for each of the processors. The problem is formulated as a 0-1 Integer Linear Programming (ILP) problem. To reduce the complexity of the ILP formulation, inferior ASIP configurations are efficiently pruned so that the solution could be reached quickly. Given a system runtime constraint, the proposed methodology finds a design with minimal area. We integrated this design methodology into a commercial design flow, and performed a case study upon the JPEG encoding application. We obtained 15 optimal designs subject to 15 different runtime constraints, each in less than 100 seconds from more than 4.2 x 1013 design points.
流应用程序可以通过处理器的管道来实现。流水线中的每个处理器都可以是应用特定指令集处理器(ASIP)，其结果是异构流水线MPSoC系统。由于api可以具有不同的配置，因此为多处理器体系结构找到最优的配置集是一个难题。在本文中，我们得到了一组执行多媒体应用的处理器的最优系统设计。系统中的变量是不同附加指令的存在与否，以及每个处理器的不同缓存配置。该问题被表述为一个0-1整数线性规划(ILP)问题。为了降低ILP制定的复杂性，可以有效地修剪较差的ASIP配置，以便快速得到解决方案。给定一个系统运行时约束，所提出的方法找到一个最小面积的设计。我们将这种设计方法集成到一个商业设计流程中，并对JPEG编码应用程序进行了案例研究。我们从超过4.2 x 1013个设计点中获得了15个受15种不同运行时约束的最佳设计，每个设计在不到100秒的时间内完成。
{"title":"Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study","authors":"Haris Javaid, S. Parameswaran","doi":"10.1145/1450135.1450137","DOIUrl":"https://doi.org/10.1145/1450135.1450137","url":null,"abstract":"Streaming applications can be implemented with a pipeline of processors. Each processor in the pipeline can be an application Specific Instruction Set Processor (ASIP) with the result being a heterogeneous pipelined MPSoC system. Since ASIPs can be of differing configurations, finding the optimal set of configurations for a multiprocessor architecture is a difficult problem.\u0000 In this paper, we obtain an optimal system design for a set of processors which execute a multimedia application. The variables in the system are the presence or absence of different additional instructions and differing cache configurations for each of the processors. The problem is formulated as a 0-1 Integer Linear Programming (ILP) problem. To reduce the complexity of the ILP formulation, inferior ASIP configurations are efficiently pruned so that the solution could be reached quickly. Given a system runtime constraint, the proposed methodology finds a design with minimal area. We integrated this design methodology into a commercial design flow, and performed a case study upon the JPEG encoding application. We obtained 15 optimal designs subject to 15 different runtime constraints, each in less than 100 seconds from more than 4.2 x 1013 design points.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128091220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of SystemC by a mapping from SystemC designs into the well-defined semantics of Uppaal timed automata. The informally defined behavior and the structure of SystemC designs are completely preserved in the generated Uppaal models. The resulting Uppaal models allow us to use the Uppaal model checker and the Uppaal tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice.
{"title":"Model checking SystemC designs using timed automata","authors":"Paula Herber, Joachim Fellmuth, S. Glesner","doi":"10.1145/1450135.1450166","DOIUrl":"https://doi.org/10.1145/1450135.1450166","url":null,"abstract":"SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of SystemC by a mapping from SystemC designs into the well-defined semantics of Uppaal timed automata. The informally defined behavior and the structure of SystemC designs are completely preserved in the generated Uppaal models. The resulting Uppaal models allow us to use the Uppaal model checker and the Uppaal tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115190064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matthias Krause, Dominik Englert, O. Bringmann, W. Rosenstiel
Instruction set simulation and real time operating system modeling have become important issues for the design of distributed embedded systems. This paper presents a holistic approach to simulate a distributed, embedded system that includes target software, processing units, and abstract RTOS within a virtual prototype environment. The processing unit is modeled by an ISS, which is embedded in a SystemC environment to allow the integration into a platform model. In comparison to existing approaches, the RTOS is not directly running on the ISS but outsourced and replaced by an RTOS model. This step strongly reduces simulation time since the execution on the ISS is much more time consuming in contrast to the execution on the host processor. The results show the theoretical and measured performance gain depending on the RTOS scheduler and task switching.
{"title":"Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation","authors":"Matthias Krause, Dominik Englert, O. Bringmann, W. Rosenstiel","doi":"10.1145/1450135.1450168","DOIUrl":"https://doi.org/10.1145/1450135.1450168","url":null,"abstract":"Instruction set simulation and real time operating system modeling have become important issues for the design of distributed embedded systems. This paper presents a holistic approach to simulate a distributed, embedded system that includes target software, processing units, and abstract RTOS within a virtual prototype environment. The processing unit is modeled by an ISS, which is embedded in a SystemC environment to allow the integration into a platform model. In comparison to existing approaches, the RTOS is not directly running on the ISS but outsourced and replaced by an RTOS model. This step strongly reduces simulation time since the execution on the ISS is much more time consuming in contrast to the execution on the host processor. The results show the theoretical and measured performance gain depending on the RTOS scheduler and task switching.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115526570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the processor is switched to low-power mode in it. We extend the previous proposed approach in two dimensions. i) We develop static analysis for the PICA technique and present optimum parameters for five common types of loops based on steady-state analysis. ii) We show that software only control is unable to guarantee its correctness in a varying runtime environment, potentially causing deadlocks. We enhance the robustness of PICA with minimal hardware extension, ensuring correct execution for any loops and parameters, which greatly facilitates exploration based parameter optimization. The combined use of our static analysis and exploration based fine-tuning makes the PICA technique applicable, to any memory-bound loop, with energy reduction. We validate our analytical models against simulation based optimization and also show through our experiments on embedded application benchmarks, that our technique can be applied to a wide range of loops with average 20% energy reductions compared to executions without PICA.
{"title":"Static analysis of processor stall cycle aggregation","authors":"Jongeun Lee, Aviral Shrivastava","doi":"10.1145/1450135.1450143","DOIUrl":"https://doi.org/10.1145/1450135.1450143","url":null,"abstract":"Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the processor is switched to low-power mode in it. We extend the previous proposed approach in two dimensions. i) We develop static analysis for the PICA technique and present optimum parameters for five common types of loops based on steady-state analysis. ii) We show that software only control is unable to guarantee its correctness in a varying runtime environment, potentially causing deadlocks. We enhance the robustness of PICA with minimal hardware extension, ensuring correct execution for any loops and parameters, which greatly facilitates exploration based parameter optimization. The combined use of our static analysis and exploration based fine-tuning makes the PICA technique applicable, to any memory-bound loop, with energy reduction. We validate our analytical models against simulation based optimization and also show through our experiments on embedded application benchmarks, that our technique can be applied to a wide range of loops with average 20% energy reductions compared to executions without PICA.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"368 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115579079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by substituting, in the design the loop, the time-consuming simulation step with a fast timing update routine. As a result, we can significantly reduce the design time from on the order of hours/days to the order of seconds/minutes. The update algorithm is defined on the Transaction Level Model (TLM) and can be used by any design flow that invokes TLM-based optimizations. This algorithm has linear-time complexity in the program size and experimental results indicate that any loss of accuracy due to this technique is negligible (< ±1%); the benefit is a reduction in total design cycle time from several hours to a matter of seconds.
{"title":"Slack analysis in the system design loop","authors":"Girish Venkataramani, S. Goldstein","doi":"10.1145/1450135.1450189","DOIUrl":"https://doi.org/10.1145/1450135.1450189","url":null,"abstract":"We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by substituting, in the design the loop, the time-consuming simulation step with a fast timing update routine. As a result, we can significantly reduce the design time from on the order of hours/days to the order of seconds/minutes. The update algorithm is defined on the Transaction Level Model (TLM) and can be used by any design flow that invokes TLM-based optimizations. This algorithm has linear-time complexity in the program size and experimental results indicate that any loss of accuracy due to this technique is negligible (< ±1%); the benefit is a reduction in total design cycle time from several hours to a matter of seconds.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip communication architecture which determines the cooperation efficiency. Network-on-Chip (NoC) is introduced to improve communication bandwidth and power efficiency. However, traditional metallic interconnects consume significant amount of power to deliver large communication bandwidths. Optical NoCs are based on silicon optical interconnects with significant bandwidth and power advantages. Optical routers are the key enabling components of optical NoCs. This paper proposed a novel optical router architecture, ODOR, for optical NoCs based on XY routing algorithm. We compared ODOR with four other router architectures, and analyzed three aspects in details, including power consumption, optical power insertion loss, and the number of microresonators. The results show that ODOR has the lowest power consumption and losses and requires the least microresonators. ODOR has 40% less power consumption, 40% less loss, and 52% less microresonator than the full-connected crossbar. Furthermore, ODOR has a special feature which guarantees the maximum power to route a packet through a network to be a small constant number, regardless of the network size. The maximum power consumption is 0.96fJ/bit under current technology. We simulated a 6x6 2D mesh NoC based on ODOR, and showed the end-to-end delay and network throughput under different offered loads and packet sizes.
{"title":"ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip","authors":"Huaxi Gu, Jiang Xu, Zheng Wang","doi":"10.1145/1450135.1450181","DOIUrl":"https://doi.org/10.1145/1450135.1450181","url":null,"abstract":"The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip communication architecture which determines the cooperation efficiency. Network-on-Chip (NoC) is introduced to improve communication bandwidth and power efficiency. However, traditional metallic interconnects consume significant amount of power to deliver large communication bandwidths. Optical NoCs are based on silicon optical interconnects with significant bandwidth and power advantages. Optical routers are the key enabling components of optical NoCs. This paper proposed a novel optical router architecture, ODOR, for optical NoCs based on XY routing algorithm. We compared ODOR with four other router architectures, and analyzed three aspects in details, including power consumption, optical power insertion loss, and the number of microresonators. The results show that ODOR has the lowest power consumption and losses and requires the least microresonators. ODOR has 40% less power consumption, 40% less loss, and 52% less microresonator than the full-connected crossbar. Furthermore, ODOR has a special feature which guarantees the maximum power to route a packet through a network to be a small constant number, regardless of the network size. The maximum power consumption is 0.96fJ/bit under current technology. We simulated a 6x6 2D mesh NoC based on ODOR, and showed the end-to-end delay and network throughput under different offered loads and packet sizes.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131937468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a new method for deriving quantitative event information for compositional multiprocessor performance analysis. This procedure brakes down the complexity into the analysis of individual components (tasks mapped to resources) and the propagation of the timing information with the help of event models. This paper improves previous methods to derive event models in a multiprocessor system by providing tighter bounds and allowing arbitrarily shaped event models. The procedure is based on a a simple yet expressive resource model called the multiple event busy time which can be derived on the basis of classical scheduling theory -- it can therefore be provided for a large domain of scheduling policies. Our experiments show that overestimation by previous methods can be reduced significantly.
{"title":"Providing accurate event models for the analysis of heterogeneous multiprocessor systems","authors":"S. Schliecker, J. Rox, M. Ivers, R. Ernst","doi":"10.1145/1450135.1450177","DOIUrl":"https://doi.org/10.1145/1450135.1450177","url":null,"abstract":"This paper proposes a new method for deriving quantitative event information for compositional multiprocessor performance analysis. This procedure brakes down the complexity into the analysis of individual components (tasks mapped to resources) and the propagation of the timing information with the help of event models. This paper improves previous methods to derive event models in a multiprocessor system by providing tighter bounds and allowing arbitrarily shaped event models. The procedure is based on a a simple yet expressive resource model called the multiple event busy time which can be derived on the basis of classical scheduling theory -- it can therefore be provided for a large domain of scheduling policies. Our experiments show that overestimation by previous methods can be reduced significantly.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117229042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hardware technology platforms are blurring at the edges as the integration frontier, a co-design frontier, holds promise of new functionality being achieved beyond electronics and software, through photonic and fluidic technologies. The problems here are complex as one considers the multiple technology partitions and the possibilities for exploring trade-offs and so this co-design frontier is largely untamed. A co-design "box", somewhat empirical by nature, supports exploratory research interests. It is motivated by trying to merge two lines of activity: one involving electronic-software rapid-prototyping and the other involving the design and fabrication of novel non-electronic devices or structures. The expectation initially is to demonstrate from an embedded system perspective whether novel fluidic devices perform as intended. Other devices will be considered in the future. Individuals and groups working in these frontier areas have attempted to promote some degree of standardization which might help clear a path forward in support of less empirical co-design techniques. Experience with microelectronics is most often used as a model with reference to the hierarchy of leaf-cells, components, functionally-designated subsystems and defined physical and signal interfaces. Physical aspects of internet connectivity are an example of advances made at the photonics-electronics frontier using multiple signal wavelengths and command, control and communication involving software, microelectronics, photonics and signal conversion. Progress with fluidics is at an early stage and major outcomes, no less transformative than the internet in the last 20 years, will occur whether in health-care or the environment or in some other sector. Complex devices or micro-assemblies that carry electronic, photonic and fluidic signals are now made regularly. Co-design technology, while lagging seriously, has the potential to reduce exploration barriers at the integration frontier, multiplying the number of exploratory paths being pursued by an increasing number of practitioners and yielding beneficial outcomes sooner than might otherwise be expected.
{"title":"Co-design in the wilderness","authors":"D. Gale","doi":"10.1145/1450135.1450185","DOIUrl":"https://doi.org/10.1145/1450135.1450185","url":null,"abstract":"Hardware technology platforms are blurring at the edges as the integration frontier, a co-design frontier, holds promise of new functionality being achieved beyond electronics and software, through photonic and fluidic technologies. The problems here are complex as one considers the multiple technology partitions and the possibilities for exploring trade-offs and so this co-design frontier is largely untamed. A co-design \"box\", somewhat empirical by nature, supports exploratory research interests. It is motivated by trying to merge two lines of activity: one involving electronic-software rapid-prototyping and the other involving the design and fabrication of novel non-electronic devices or structures. The expectation initially is to demonstrate from an embedded system perspective whether novel fluidic devices perform as intended. Other devices will be considered in the future. Individuals and groups working in these frontier areas have attempted to promote some degree of standardization which might help clear a path forward in support of less empirical co-design techniques. Experience with microelectronics is most often used as a model with reference to the hierarchy of leaf-cells, components, functionally-designated subsystems and defined physical and signal interfaces. Physical aspects of internet connectivity are an example of advances made at the photonics-electronics frontier using multiple signal wavelengths and command, control and communication involving software, microelectronics, photonics and signal conversion. Progress with fluidics is at an early stage and major outcomes, no less transformative than the internet in the last 20 years, will occur whether in health-care or the environment or in some other sector. Complex devices or micro-assemblies that carry electronic, photonic and fluidic signals are now made regularly. Co-design technology, while lagging seriously, has the potential to reduce exploration barriers at the integration frontier, multiplying the number of exploratory paths being pursued by an increasing number of practitioners and yielding beneficial outcomes sooner than might otherwise be expected.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134289867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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