Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5955003
N. R. Potlapally
Computing platforms used in practice are complex and require interaction between multiple hardware components (such as processor, chipset, memory and peripherals) for their normal operation. Maintaining security of these computing platforms translates to verifying there are no known security exploits present in the run-time interaction between these hardware units which can be exploited by attackers. However, given the large number of state elements in the hardware units and many control signals influencing their mutual interaction, validating security of a commercial computing platform thoroughly can be complicated and intractable. We believe this real-world perspective of hardware security is crucial to building secure systems in practice, but it has not been sufficiently addressed in security research community, and our paper is a step in covering this gap. In this paper, we exemplify the challenges in correctly implementing security in commercial hardware platforms through representative examples of various classes of hardware-oriented security attacks. We present an overview of methods adopted to deal with the complexity of validating security of hardware in an industrial setting, and enumerate opportunities present for the security research community to contribute to hardware security validation.
{"title":"Hardware security in practice: Challenges and opportunities","authors":"N. R. Potlapally","doi":"10.1109/HST.2011.5955003","DOIUrl":"https://doi.org/10.1109/HST.2011.5955003","url":null,"abstract":"Computing platforms used in practice are complex and require interaction between multiple hardware components (such as processor, chipset, memory and peripherals) for their normal operation. Maintaining security of these computing platforms translates to verifying there are no known security exploits present in the run-time interaction between these hardware units which can be exploited by attackers. However, given the large number of state elements in the hardware units and many control signals influencing their mutual interaction, validating security of a commercial computing platform thoroughly can be complicated and intractable. We believe this real-world perspective of hardware security is crucial to building secure systems in practice, but it has not been sufficiently addressed in security research community, and our paper is a step in covering this gap. In this paper, we exemplify the challenges in correctly implementing security in commercial hardware platforms through representative examples of various classes of hardware-oriented security attacks. We present an overview of methods adopted to deal with the complexity of validating security of hardware in an industrial setting, and enumerate opportunities present for the security research community to contribute to hardware security validation.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128212485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5955011
Qingqing Chen, G. Csaba, P. Lugli, Ulf Schlichtmann, U. Rührmair
This paper introduces a new architecture for circuit-based Physical Unclonable Functions (PUFs) which we call the Bistable Ring PUF (BR-PUF). Based on experimental results obtained from FPGA-based implementations of the BR-PUF, the quality of this new design is discussed in different aspects, including uniqueness and reliability. On the basis of the observed complexity in the challenge-response behavior of BR-PUFs, we argue that this new PUF could be a promising candidate for Strong PUFs. Our design shows noticeable temperature sensitivity, but we discuss how this problem can be addressed by additional hardware and protocol measures.
{"title":"The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions","authors":"Qingqing Chen, G. Csaba, P. Lugli, Ulf Schlichtmann, U. Rührmair","doi":"10.1109/HST.2011.5955011","DOIUrl":"https://doi.org/10.1109/HST.2011.5955011","url":null,"abstract":"This paper introduces a new architecture for circuit-based Physical Unclonable Functions (PUFs) which we call the Bistable Ring PUF (BR-PUF). Based on experimental results obtained from FPGA-based implementations of the BR-PUF, the quality of this new design is discussed in different aspects, including uniqueness and reliability. On the basis of the observed complexity in the challenge-response behavior of BR-PUFs, we argue that this new PUF could be a promising candidate for Strong PUFs. Our design shows noticeable temperature sensitivity, but we discuss how this problem can be addressed by additional hardware and protocol measures.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122198231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5955013
Yang Li, K. Ohta, K. Sakiyama
This paper revisits and improves the fault sensitivity analysis (FSA) attack on WDDL-AES. At CHES 2010, the FSA attack on WDDL-AES was proposed by Li et al. based on the delay timing difference for complementary wires. In their attack, the vulnerability of WDDL-AES mainly comes from the implementation deficiency rather than the WDDL technique itself. On the contrary, we explain that a well-implemented WDDL-AES also has the vulnerability against the FSA attack due to the input-data dependency for the critical delay of the WDDL S-box. We explain the observed ciphertext-bit dependency for the fault sensitivity (FS) data when the clock glitch is injected at the final AES round. By proposing a new distinguisher, our FSA attack can successfully retrieve the secret key information for WDDL-AES on SASEBO-R.
{"title":"Revisit fault sensitivity analysis on WDDL-AES","authors":"Yang Li, K. Ohta, K. Sakiyama","doi":"10.1109/HST.2011.5955013","DOIUrl":"https://doi.org/10.1109/HST.2011.5955013","url":null,"abstract":"This paper revisits and improves the fault sensitivity analysis (FSA) attack on WDDL-AES. At CHES 2010, the FSA attack on WDDL-AES was proposed by Li et al. based on the delay timing difference for complementary wires. In their attack, the vulnerability of WDDL-AES mainly comes from the implementation deficiency rather than the WDDL technique itself. On the contrary, we explain that a well-implemented WDDL-AES also has the vulnerability against the FSA attack due to the input-data dependency for the critical delay of the WDDL S-box. We explain the observed ciphertext-bit dependency for the fault sensitivity (FS) data when the clock glitch is injected at the final AES round. By proposing a new distinguisher, our FSA attack can successfully retrieve the secret key information for WDDL-AES on SASEBO-R.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117008273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5955009
H. Handschuh
Physical Unclonable Functions originate in intrinsic properties extracted from devices and objects for the purpose of identification. They can take many forms among which the most common ones are optical PUFs, paper PUFs, coating PUFs and silicon PUFs. In order to identify silicon devices, further variants include PUFs based on delays in a silicon circuitry such as arbiter PUFs and ring-oscillator PUFs, and PUFs based on the start-up behavior of memory cells such as SRAM PUFs, butterfly PUFs and flip-flop PUFs.
{"title":"Hardware intrinsic security based on SRAM PUFs: Tales from the industry","authors":"H. Handschuh","doi":"10.1109/HST.2011.5955009","DOIUrl":"https://doi.org/10.1109/HST.2011.5955009","url":null,"abstract":"Physical Unclonable Functions originate in intrinsic properties extracted from devices and objects for the purpose of identification. They can take many forms among which the most common ones are optical PUFs, paper PUFs, coating PUFs and silicon PUFs. In order to identify silicon devices, further variants include PUFs based on delays in a silicon circuitry such as arbiter PUFs and ring-oscillator PUFs, and PUFs based on the start-up behavior of memory cells such as SRAM PUFs, butterfly PUFs and flip-flop PUFs.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131222486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5955007
P. Song, F. Stellari, D. Pfeiffer, Jim Culp, A. Weger, A. Bonnoit, B. Wisnieff, M. Taubenblatt
This paper presents a new technique for detecting chip alterations using intrinsic light emission in combination with electrical test. The key idea of this method is based on the fact that any active device emits infrared light emission when it is powered on. High sensitivity photon detectors can be employed to capture the weak emission while the chip under test is powered on and electric stimuli are applied to it. In particular, two main families of electrical test modes, static and dynamic, can be applied. Positive results of the application of this methodology as well as key challenges will be discussed in the paper, including spatial resolution, imaging processing, data interpretation, etc.
{"title":"MARVEL — Malicious alteration recognition and verification by emission of light","authors":"P. Song, F. Stellari, D. Pfeiffer, Jim Culp, A. Weger, A. Bonnoit, B. Wisnieff, M. Taubenblatt","doi":"10.1109/HST.2011.5955007","DOIUrl":"https://doi.org/10.1109/HST.2011.5955007","url":null,"abstract":"This paper presents a new technique for detecting chip alterations using intrinsic light emission in combination with electrical test. The key idea of this method is based on the fact that any active device emits infrared light emission when it is powered on. High sensitivity photon detectors can be employed to capture the weak emission while the chip under test is powered on and electric stimuli are applied to it. In particular, two main families of electrical test modes, static and dynamic, can be applied. Positive results of the application of this methodology as well as key challenges will be discussed in the paper, including spatial resolution, imaging processing, data interpretation, etc.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130079963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5954991
Katsuhiko Iwai, M. Shiozaki, Anh-Tuan Hoang, Kenji Kojima, T. Fujino
Differential Power Analysis (DPA) which is one of the Side-Channel Attack techniques can easily extract the secret information such as a cryptographic key from the device by analyzing the power consumption. Some DPA-resistant techniques have been proposed to protect the secret information. However, these techniques require special CADs, which balance wiring capacitance and control the timing to activate the logics for enabling signals. We have proposed a DPA-resistant Domino-RSL technique to design and implement by the standard CAD tool easily. This DPA resistance is achieved by eliminating the correlation between power consumption and cryptography operation. In this paper, the design flow of the Domino-RSL technique is presented and the DPA resistance of a DES circuit, which was designed and fabricated with 0.18μm CMOS technology, is evaluated using the Side-channel Attack Standard Evaluation Board (SASEBO). The Domino-RSL DES circuit did never reveal the secret key even with 100,000 wave samples analysis.
{"title":"Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL","authors":"Katsuhiko Iwai, M. Shiozaki, Anh-Tuan Hoang, Kenji Kojima, T. Fujino","doi":"10.1109/HST.2011.5954991","DOIUrl":"https://doi.org/10.1109/HST.2011.5954991","url":null,"abstract":"Differential Power Analysis (DPA) which is one of the Side-Channel Attack techniques can easily extract the secret information such as a cryptographic key from the device by analyzing the power consumption. Some DPA-resistant techniques have been proposed to protect the secret information. However, these techniques require special CADs, which balance wiring capacitance and control the timing to activate the logics for enabling signals. We have proposed a DPA-resistant Domino-RSL technique to design and implement by the standard CAD tool easily. This DPA resistance is achieved by eliminating the correlation between power consumption and cryptography operation. In this paper, the design flow of the Domino-RSL technique is presented and the DPA resistance of a DES circuit, which was designed and fabricated with 0.18μm CMOS technology, is evaluated using the Side-channel Attack Standard Evaluation Board (SASEBO). The Domino-RSL DES circuit did never reveal the secret key even with 100,000 wave samples analysis.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"21 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131844254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5954990
Mathilde Soucarros, Cécile Canovas, J. Clédière, P. Elbaz-Vincent, Denis Réal
Today TRNGs are used in many different applications. The quality of their randomness is determined by these applications: for example those with security requirements need very good random numbers while simulations have fewer constraints on their properties. It is therefore necessary to investigate their robustness when under stress, being due to extreme conditions of utilization or deliberates attacks. Many TRNG designs exist and we decided to investigate two randomness sources and two post-processors that are commonly found in the literature. These TRNGs were implemented into a chip and put under test with variations of their temperature. The behavior of the randomness sources and the efficiency of the post-processors are evaluated thanks to several standard statistical tests presented in the literature.
{"title":"Influence of the temperature on true random number generators","authors":"Mathilde Soucarros, Cécile Canovas, J. Clédière, P. Elbaz-Vincent, Denis Réal","doi":"10.1109/HST.2011.5954990","DOIUrl":"https://doi.org/10.1109/HST.2011.5954990","url":null,"abstract":"Today TRNGs are used in many different applications. The quality of their randomness is determined by these applications: for example those with security requirements need very good random numbers while simulations have fewer constraints on their properties. It is therefore necessary to investigate their robustness when under stress, being due to extreme conditions of utilization or deliberates attacks. Many TRNG designs exist and we decided to investigate two randomness sources and two post-processors that are commonly found in the literature. These TRNGs were implemented into a chip and put under test with variations of their temperature. The behavior of the randomness sources and the efficiency of the post-processors are evaluated thanks to several standard statistical tests presented in the literature.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115935618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5955015
Alessandro Barenghi, G. Bertoni, A. Palomba, Ruggero Susella
A novel fault attack against ECDSA is proposed in this work. It allows to retrieve the secret signing key, by means of injecting faults during the computation of the signature primitive. The proposed method relies on faults injected during a multiplication employed to perform the signature recombination at the end of the ECDSA signing algorithm. Exploiting the faulty signatures, it is possible to reduce the size of the group of the discrete logarithm problem warranting the security margin up to a point where it is computationally treatable. The amount of faulty signatures requested to perform the attack is relatively small, ranging from 4 to a few tenths. The key retrieval can be applied to any key length, like those standardised by NIST, including the ones mandated for top secret documents by NSA suite B. The required post processing of the obtained faulty values is practical on a common consumer grade desktop. The procedure does not rely on any particular structure of the employed curve and may easily be extended to the regular DSA based on modular arithmetics.
{"title":"A novel fault attack against ECDSA","authors":"Alessandro Barenghi, G. Bertoni, A. Palomba, Ruggero Susella","doi":"10.1109/HST.2011.5955015","DOIUrl":"https://doi.org/10.1109/HST.2011.5955015","url":null,"abstract":"A novel fault attack against ECDSA is proposed in this work. It allows to retrieve the secret signing key, by means of injecting faults during the computation of the signature primitive. The proposed method relies on faults injected during a multiplication employed to perform the signature recombination at the end of the ECDSA signing algorithm. Exploiting the faulty signatures, it is possible to reduce the size of the group of the discrete logarithm problem warranting the security margin up to a point where it is computationally treatable. The amount of faulty signatures requested to perform the attack is relatively small, ranging from 4 to a few tenths. The key retrieval can be applied to any key length, like those standardised by NIST, including the ones mandated for top secret documents by NSA suite B. The required post processing of the obtained faulty values is practical on a common consumer grade desktop. The procedure does not rely on any particular structure of the employed curve and may easily be extended to the regular DSA based on modular arithmetics.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"550 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116439848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/HST.2011.5955008
K. Gotze
This paper summarizes the high level approach taken to security validation by design teams at a CPU Semiconductor manufacturer from architecture, through design, simulation and post-si testing. We review several functional areas that in our experience frequently yield vulnerabilities, describe some of the issues commonly found there, and touch on why these areas can be problematic. By highlighting these issues we hope to encourage future work in academia and industry on techniques to better find, mitigate, or prevent these problems.
{"title":"A survey of frequently identified vulnerabilities in commercial computing semiconductors","authors":"K. Gotze","doi":"10.1109/HST.2011.5955008","DOIUrl":"https://doi.org/10.1109/HST.2011.5955008","url":null,"abstract":"This paper summarizes the high level approach taken to security validation by design teams at a CPU Semiconductor manufacturer from architecture, through design, simulation and post-si testing. We review several functional areas that in our experience frequently yield vulnerabilities, describe some of the issues commonly found there, and touch on why these areas can be problematic. By highlighting these issues we hope to encourage future work in academia and industry on techniques to better find, mitigate, or prevent these problems.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-01DOI: 10.1109/HST.2011.5954988
Eric Love, Yier Jin, Y. Makris
We introduce a novel hardware intellectual property acquisition protocol, show how it can support the transfer of provably trustworthy modules between hardware IP producers and consumers, and discuss what it might mean for a device to be considered “secure.” Specifically, we demonstrate the applicability of previous work in the software field of Proof-Carrying Code (PCC) to the problem of hardware trust and use it to combat the threat of hardware IP-level Trojans. We outline a semantic model representing the constructs permissible in a Verilog hardware description language (HDL) and show how this model can be used to reason about the trustworthiness of circuits represented at the register-transfer level (RTL). A discussion of “security-related properties” reveals how rules for trustworthy operation might be established for a particular design without necessarily specifying exact functionality. We then examine a hypothetical scenario involving a consumer with certain security needs and show how our system could be employed to guarantee that these needs are met by a hardware IP vendor's code.
{"title":"Enhancing security via provably trustworthy hardware intellectual property","authors":"Eric Love, Yier Jin, Y. Makris","doi":"10.1109/HST.2011.5954988","DOIUrl":"https://doi.org/10.1109/HST.2011.5954988","url":null,"abstract":"We introduce a novel hardware intellectual property acquisition protocol, show how it can support the transfer of provably trustworthy modules between hardware IP producers and consumers, and discuss what it might mean for a device to be considered “secure.” Specifically, we demonstrate the applicability of previous work in the software field of Proof-Carrying Code (PCC) to the problem of hardware trust and use it to combat the threat of hardware IP-level Trojans. We outline a semantic model representing the constructs permissible in a Verilog hardware description language (HDL) and show how this model can be used to reason about the trustworthiness of circuits represented at the register-transfer level (RTL). A discussion of “security-related properties” reveals how rules for trustworthy operation might be established for a particular design without necessarily specifying exact functionality. We then examine a hypothetical scenario involving a consumer with certain security needs and show how our system could be employed to guarantee that these needs are met by a hardware IP vendor's code.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127944835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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