We focus on the non-conflicting design of a multistage feedforward network with optical bufferless Switch and fiber Delay Lines (SDL) to emulate an N-to-1 output buffered multiplexer supporting variable length bursts. Y. T. Chen et al. presented a sufficient condition (a bound) to guarantee the non-conflicting and FIFO properties in such a design. In this paper, we first point out the upper bound can not rise infinitely with the increase of the maximum burst length. Then, we develop a framework to construct a case which can be used to achieve a lower bound. Through simulation and performance comparison, we find the new bounds can significantly decrease the hardware cost for constructing such a feedforward SDL multiplexer while still providing the same performance guarantee as that of the old one.
我们专注于光无缓冲开关和光纤延迟线(SDL)的多级前馈网络的无冲突设计，以模拟支持可变长度突发的n对1输出缓冲多路复用器。Y. T. Chen等人提出了一个充分条件(界)来保证这种设计的不冲突和FIFO特性。本文首先指出，随着最大突发长度的增加，其上界不能无限上升。然后，我们开发了一个框架来构造一个可以用来实现下界的情况。通过仿真和性能比较，我们发现新的边界可以显著降低构建这种前馈SDL多路复用器的硬件成本，同时仍然提供与旧边界相同的性能保证。
{"title":"Improved Bounds on the Feedfoward Design of Optical Multiplexers","authors":"Xiaoliang Wang, Xiaohong Jiang, S. Horiguchi","doi":"10.1109/I-SPAN.2008.10","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.10","url":null,"abstract":"We focus on the non-conflicting design of a multistage feedforward network with optical bufferless Switch and fiber Delay Lines (SDL) to emulate an N-to-1 output buffered multiplexer supporting variable length bursts. Y. T. Chen et al. presented a sufficient condition (a bound) to guarantee the non-conflicting and FIFO properties in such a design. In this paper, we first point out the upper bound can not rise infinitely with the increase of the maximum burst length. Then, we develop a framework to construct a case which can be used to achieve a lower bound. Through simulation and performance comparison, we find the new bounds can significantly decrease the hardware cost for constructing such a feedforward SDL multiplexer while still providing the same performance guarantee as that of the old one.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131971318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Membrane computing, first introduced in 1998 by Gheorghe Paun, is a part of the general research effort of describing and investigating computing models, ideas, architectures, and paradigms from the processes taking place in nature. It is a branch of molecular computing that is motivated by cell biology. Membrane computing identifies an unconventional computing model, namely a P system, which abstracts from the way living cells process chemical compounds in their compartmental structure. Regions defined by a membrane structure contain multisets of objects that evolve according to specified rules. The objects can be represented as symbols or strings of symbols. By using the rules in a nondeterministic (deterministic) maximally parallel manner, transitions between the system configurations can be obtained. A sequence of transitions is a computation of how the system is evolving. Various ways of controlling the transfer of objects from one region to another and applying the rules, as well as possibilities to dissolve, divide or create membranes have been studied. P systems have a great potential for implementing massively concurrent systems in an efficient way that would allow us to solve currently intractable problems once future bio-technology gives way to a practical bio- realization. Since its introduction, the literature in this area has grown rapidly (in 2003, the Institute for Scientific Information designated the initialpaper as "fast breaking" and the domain as an "emerging research front in computer science"). We give a brief overview of membrane computing and report on recent results that answer some interesting and fundamental open questions in the field. We also look at the recently introduced neural-like systems, called spiking neural P systems. These systems incorporate the ideas of spiking neurons into membrane computing. We present various classes and characterize their computing power and complexity. In particular, we analyze asynchronous and sequential systems and present some conditions under which they become (non-)universal. The non-universal variants are characterized by monotonic counter machines and partially blind counter machines. The latter devices are known to be equivalent to vector addition systems (or Petri nets) and, hence, have many decidable properties.
{"title":"Computing with Cells: Membrane Systems","authors":"O. Ibarra","doi":"10.1109/I-SPAN.2008.12","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.12","url":null,"abstract":"Summary form only given. Membrane computing, first introduced in 1998 by Gheorghe Paun, is a part of the general research effort of describing and investigating computing models, ideas, architectures, and paradigms from the processes taking place in nature. It is a branch of molecular computing that is motivated by cell biology. Membrane computing identifies an unconventional computing model, namely a P system, which abstracts from the way living cells process chemical compounds in their compartmental structure. Regions defined by a membrane structure contain multisets of objects that evolve according to specified rules. The objects can be represented as symbols or strings of symbols. By using the rules in a nondeterministic (deterministic) maximally parallel manner, transitions between the system configurations can be obtained. A sequence of transitions is a computation of how the system is evolving. Various ways of controlling the transfer of objects from one region to another and applying the rules, as well as possibilities to dissolve, divide or create membranes have been studied. P systems have a great potential for implementing massively concurrent systems in an efficient way that would allow us to solve currently intractable problems once future bio-technology gives way to a practical bio- realization. Since its introduction, the literature in this area has grown rapidly (in 2003, the Institute for Scientific Information designated the initialpaper as \"fast breaking\" and the domain as an \"emerging research front in computer science\"). We give a brief overview of membrane computing and report on recent results that answer some interesting and fundamental open questions in the field. We also look at the recently introduced neural-like systems, called spiking neural P systems. These systems incorporate the ideas of spiking neurons into membrane computing. We present various classes and characterize their computing power and complexity. In particular, we analyze asynchronous and sequential systems and present some conditions under which they become (non-)universal. The non-universal variants are characterized by monotonic counter machines and partially blind counter machines. The latter devices are known to be equivalent to vector addition systems (or Petri nets) and, hence, have many decidable properties.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125089026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We compare the performance of three handoff protocols, namely Mobile IP, Fast Handoff and mSCTP. Among the three schemes, Mobile IP suffers from the lowest data throughput and longest handoff latency. Fast Handoff can perform better, provided that the mobile node can handoff to the new base station at an appropriate time instant when data forwarding between network routers begins. mSCTP supports multihoming; the mobile node does not need to determine the exact handoff time. Nevertheless, packet reordering and the subsequent fast retransmission degrades its handoff performance. To avoid these problems, adding some flow control operations in the transport layer is necessary. Flow control should be carried out in-sync with the handoff operations. This implies the transport layer should additionally recognise when do the handoff procedures start or finish. We therefore come up with a natural choice in designing a handoff scheme, which is to centralise the handoff and flow control operations in the transport layer.
{"title":"Handoff Performance Comparison of Mobile IP, Fast Handoff and mSCTP in Mobile Wireless Networks","authors":"Ken C. K. Tsang, Cho-Li Wang, F. Lau","doi":"10.1109/I-SPAN.2008.43","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.43","url":null,"abstract":"We compare the performance of three handoff protocols, namely Mobile IP, Fast Handoff and mSCTP. Among the three schemes, Mobile IP suffers from the lowest data throughput and longest handoff latency. Fast Handoff can perform better, provided that the mobile node can handoff to the new base station at an appropriate time instant when data forwarding between network routers begins. mSCTP supports multihoming; the mobile node does not need to determine the exact handoff time. Nevertheless, packet reordering and the subsequent fast retransmission degrades its handoff performance. To avoid these problems, adding some flow control operations in the transport layer is necessary. Flow control should be carried out in-sync with the handoff operations. This implies the transport layer should additionally recognise when do the handoff procedures start or finish. We therefore come up with a natural choice in designing a handoff scheme, which is to centralise the handoff and flow control operations in the transport layer.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115671663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Safaei, A. Khonsari, Aresh Dadlani, M. Ould-Khaoua
With increase in concern for reliability in the current and next generation of multiprocessors system-on-chip (MP-SoCs), multi-computers, cluster computers, and peer-to-peer communication networks, fault-tolerance has become an integral part of these systems. One of the fundamental issues regarding fault-tolerance is how to efficiently route a faulty network where each component is associated with some probability of failure. Adaptive fault-tolerant routing algorithms have been frequently suggested in the literature as means of improving communication performance and fault-tolerant demands in computer systems. Also, several results have been reported on usage of fault rings in providing detours to messages blocked by faults and in routing messages adaptively around the rectangular faulty regions. In order to analyze the performance of such routing schemes, one must investigate the characteristics of fault rings. In this paper, we derive mathematical expressions to compute the probability of message facing the fault rings in the well-known mesh interconnection network. We also conduct extensive simulation experiments using a variety of faults, the results of which are used to confirm the accuracy of the proposed models.
{"title":"A Probabilistic Characterization of Fault Rings in Adaptively-Routed Mesh Interconnection Networks","authors":"F. Safaei, A. Khonsari, Aresh Dadlani, M. Ould-Khaoua","doi":"10.1109/I-SPAN.2008.17","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.17","url":null,"abstract":"With increase in concern for reliability in the current and next generation of multiprocessors system-on-chip (MP-SoCs), multi-computers, cluster computers, and peer-to-peer communication networks, fault-tolerance has become an integral part of these systems. One of the fundamental issues regarding fault-tolerance is how to efficiently route a faulty network where each component is associated with some probability of failure. Adaptive fault-tolerant routing algorithms have been frequently suggested in the literature as means of improving communication performance and fault-tolerant demands in computer systems. Also, several results have been reported on usage of fault rings in providing detours to messages blocked by faults and in routing messages adaptively around the rectangular faulty regions. In order to analyze the performance of such routing schemes, one must investigate the characteristics of fault rings. In this paper, we derive mathematical expressions to compute the probability of message facing the fault rings in the well-known mesh interconnection network. We also conduct extensive simulation experiments using a variety of faults, the results of which are used to confirm the accuracy of the proposed models.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As system-on-chip (SoCs) become more complex, high performance interconnection mediums are required to handle their complexity. Network-on-chips (NoCs) enable integration of more intellectual properties (IPs) into the SoC with increased performance. In the recent MARTE (modeling and analysis of real-time and embedded systems) profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topologies. This paper presents a modeling methodology based on that notation to model the delta network family of interconnection networks for NoC construction.
{"title":"Using an MDE Approach for Modeling of Interconnection Networks","authors":"I. Quadri, Pierre Boulet, S. Meftali, J. Dekeyser","doi":"10.1109/I-SPAN.2008.40","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.40","url":null,"abstract":"As system-on-chip (SoCs) become more complex, high performance interconnection mediums are required to handle their complexity. Network-on-chips (NoCs) enable integration of more intellectual properties (IPs) into the SoC with increased performance. In the recent MARTE (modeling and analysis of real-time and embedded systems) profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topologies. This paper presents a modeling methodology based on that notation to model the delta network family of interconnection networks for NoC construction.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-dimensional network-on-chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and trees have been used for NoCs. In particular, much attention has been focused on tree-based topologies, such as fat trees and fat H-tree, because of their relatively short hop-count that enables lower latency communication compared to meshes or tori. However, since on-chip tree-based networks in their 2-D layouts have long wire links around the root, they generate serious wire delay, posing severe problems to modem VLSI design. In this paper, we propose a 3-D layout scheme of trees including Fat Trees and fat H-tree for 3-D ICs in order to resolve the trees' intrinsic disadvantage. The 3-D layouts are compared with the original 2-D layouts in terms of network logic area, wire length, wire delay, number of repeaters inserted, and energy consumption. Evaluation results show that 1) total wire length is reduced by 25.0% to 50.0%; 2) wire delay is improved and repeater buffers that consume considerable energy can be removed; 3) flit transmission energy is reduced by up to 47.0%; 4) area overhead is at most 7.8%, which compares favorably to those for 3-D mesh and torus.
{"title":"Three-Dimensional Layout of On-Chip Tree-Based Networks","authors":"Hiroki Matsutani, M. Koibuchi, D. Hsu, H. Amano","doi":"10.1109/I-SPAN.2008.39","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.39","url":null,"abstract":"Three-dimensional network-on-chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and trees have been used for NoCs. In particular, much attention has been focused on tree-based topologies, such as fat trees and fat H-tree, because of their relatively short hop-count that enables lower latency communication compared to meshes or tori. However, since on-chip tree-based networks in their 2-D layouts have long wire links around the root, they generate serious wire delay, posing severe problems to modem VLSI design. In this paper, we propose a 3-D layout scheme of trees including Fat Trees and fat H-tree for 3-D ICs in order to resolve the trees' intrinsic disadvantage. The 3-D layouts are compared with the original 2-D layouts in terms of network logic area, wire length, wire delay, number of repeaters inserted, and energy consumption. Evaluation results show that 1) total wire length is reduced by 25.0% to 50.0%; 2) wire delay is improved and repeater buffers that consume considerable energy can be removed; 3) flit transmission energy is reduced by up to 47.0%; 4) area overhead is at most 7.8%, which compares favorably to those for 3-D mesh and torus.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125434059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-07DOI: 10.1142/S0219265909002698
Z. Zaidi, Sara Hakami, T. Moors, B. Landfeldt
Anomaly detection is becoming a powerful and necessary component as wireless networks gain popularity. In this paper, we evaluate the efficacy of PCA based anomaly detection for wireless mesh networks. PCA was originally developed for wired networks. Our experiments show that it is possible to detect different types of anomalies in an interference prone wireless environment. However, the sensitivity of PCA to small changes in flows prompted us to develop an anomaly identification scheme which automatically identifies the flow(s) causing the detected anomaly and their contributions in terms of number of packets. Our results show that the identification scheme is able to differentiate false alarms from real anomalies and pinpoint the culprit(s) in case of a real fault or threat. The experiments were performed over an 8 node mesh testbed deployed in an urban street layout in Sydney, under different realistic traffic scenarios. Our identification scheme facilitates the use of PCA based method for real-time anomaly detection in wireless networks as it can filter the false alarms locally at the monitoring nodes without excessive computational overhead.
{"title":"Detection and Identification of Anomalies in Wireless Mesh Networks Using Principal Component Analysis (PCA)","authors":"Z. Zaidi, Sara Hakami, T. Moors, B. Landfeldt","doi":"10.1142/S0219265909002698","DOIUrl":"https://doi.org/10.1142/S0219265909002698","url":null,"abstract":"Anomaly detection is becoming a powerful and necessary component as wireless networks gain popularity. In this paper, we evaluate the efficacy of PCA based anomaly detection for wireless mesh networks. PCA was originally developed for wired networks. Our experiments show that it is possible to detect different types of anomalies in an interference prone wireless environment. However, the sensitivity of PCA to small changes in flows prompted us to develop an anomaly identification scheme which automatically identifies the flow(s) causing the detected anomaly and their contributions in terms of number of packets. Our results show that the identification scheme is able to differentiate false alarms from real anomalies and pinpoint the culprit(s) in case of a real fault or threat. The experiments were performed over an 8 node mesh testbed deployed in an urban street layout in Sydney, under different realistic traffic scenarios. Our identification scheme facilitates the use of PCA based method for real-time anomaly detection in wireless networks as it can filter the false alarms locally at the monitoring nodes without excessive computational overhead.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
According to recent studies, communication networks built on extremal Cayley digraphs of finite cyclic groups have many advantages over that based on n-cubes. Extremal Cayley digraphs have been studied extensively in recent years. In this paper, we prove, for every positive integer k, that the k-wide diameter of the Cayley digraph Cay(Zm, A) is at most diam(Cay(Zm, A)) + 1 if A is an "m-ideal" set of k positive integers.
{"title":"Wide Diameter of Cayley Digraphs of Finite Cyclic Groups","authors":"Xingde Jia","doi":"10.1109/I-SPAN.2008.19","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.19","url":null,"abstract":"According to recent studies, communication networks built on extremal Cayley digraphs of finite cyclic groups have many advantages over that based on n-cubes. Extremal Cayley digraphs have been studied extensively in recent years. In this paper, we prove, for every positive integer k, that the k-wide diameter of the Cayley digraph Cay(Zm, A) is at most diam(Cay(Zm, A)) + 1 if A is an \"m-ideal\" set of k positive integers.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130614450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Overlay multicast protocols construct a virtual mesh spanning all member nodes of a multicast group. It employs standard unicast routing and forwarding to fulfill multicast functionality. The advantages of this approach are robustness and low overhead. However, efficiency and stability are the issues that must be addressed in the mobile ad hoc network (MANET) environment. In this paper, we propose an effective structure for overlay multicast to solve these problems in MANET. Instead of using a spanning tree on the virtual mesh, we introduce a simple structure called k- tree trunk for multicast. A k-tree trunk of a tree is a subtree with k leaves that minimizes the sum of the distances of all vertices to the subtree plus the size of the subtree. The k-tree trunk is more stable and easier to maintain than the spanning tree in MANET. The simulation results show that our approach handles the flexibility and mobility issues in an overlay multicast protocol effectively, especially when the group size is large.
{"title":"K-Tree Trunk and a Distributed Algorithm for Effective Overlay Multicast on Mobile Ad Hoc Networks","authors":"Yamin Li, S. Peng, Wanming Chu","doi":"10.1109/I-SPAN.2008.22","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.22","url":null,"abstract":"Overlay multicast protocols construct a virtual mesh spanning all member nodes of a multicast group. It employs standard unicast routing and forwarding to fulfill multicast functionality. The advantages of this approach are robustness and low overhead. However, efficiency and stability are the issues that must be addressed in the mobile ad hoc network (MANET) environment. In this paper, we propose an effective structure for overlay multicast to solve these problems in MANET. Instead of using a spanning tree on the virtual mesh, we introduce a simple structure called k- tree trunk for multicast. A k-tree trunk of a tree is a subtree with k leaves that minimizes the sum of the distances of all vertices to the subtree plus the size of the subtree. The k-tree trunk is more stable and easier to maintain than the spanning tree in MANET. The simulation results show that our approach handles the flexibility and mobility issues in an overlay multicast protocol effectively, especially when the group size is large.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134393902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been proposed in the last few years to reduce data access latency by taking advantage of multi-core architectures. In this paper, we propose a taxonomy that classifies various design concerns in developing a prefetching strategy. We discuss various prefetching strategies and issues that have to be considered in designing a prefetching strategy for multi-core processors.
{"title":"A Taxonomy of Data Prefetching Mechanisms","authors":"S. Byna, Yong Chen, Xian-He Sun","doi":"10.1109/I-SPAN.2008.24","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.24","url":null,"abstract":"Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been proposed in the last few years to reduce data access latency by taking advantage of multi-core architectures. In this paper, we propose a taxonomy that classifies various design concerns in developing a prefetching strategy. We discuss various prefetching strategies and issues that have to be considered in designing a prefetching strategy for multi-core processors.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128932171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：